<div dir="ltr"><div>Both are<br><br></div>Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Mar 21, 2017 at 2:57 PM, Anuj Phogat <span dir="ltr"><<a href="mailto:anuj.phogat@gmail.com" target="_blank">anuj.phogat@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Yf/Ys tiling never got used in i965 due to not delivering<br>
the expected performance benefits. So, this patch is deleting<br>
this dead code in favor of adding it later in ISL when we<br>
actually find it useful. ISL can then share this code between<br>
vulkan and GL.<br>
<br>
Signed-off-by: Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com">anuj.phogat@gmail.com</a>><br>
Cc: Kenneth Graunke <<a href="mailto:kenneth@whitecape.org">kenneth@whitecape.org</a>><br>
---<br>
src/mesa/drivers/dri/i965/brw_<wbr>defines.h | 9 --<br>
src/mesa/drivers/dri/i965/brw_<wbr>misc_state.c | 3 +-<br>
src/mesa/drivers/dri/i965/brw_<wbr>tex_layout.c | 130 -----------------------<br>
src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c | 143 ++++++--------------------<br>
src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.h | 17 +--<br>
5 files changed, 35 insertions(+), 267 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_defines.h b/src/mesa/drivers/dri/i965/<wbr>brw_defines.h<br>
index efed5a6..08106c0 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_defines.h<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_defines.h<br>
@@ -354,12 +354,6 @@<br>
#define GEN7_SURFACE_MOCS_SHIFT 16<br>
#define GEN7_SURFACE_MOCS_MASK INTEL_MASK(19, 16)<br>
<br>
-#define GEN9_SURFACE_TRMODE_SHIFT 18<br>
-#define GEN9_SURFACE_TRMODE_MASK INTEL_MASK(19, 18)<br>
-#define GEN9_SURFACE_TRMODE_NONE 0<br>
-#define GEN9_SURFACE_TRMODE_TILEYF 1<br>
-#define GEN9_SURFACE_TRMODE_TILEYS 2<br>
-<br>
#define GEN9_SURFACE_MIP_TAIL_START_<wbr>LOD_SHIFT 8<br>
#define GEN9_SURFACE_MIP_TAIL_START_<wbr>LOD_MASK INTEL_MASK(11, 8)<br>
<br>
@@ -1620,9 +1614,6 @@ enum brw_pixel_shader_coverage_<wbr>mask_mode {<br>
#define BR13_16161616 (0x4 << 24)<br>
#define BR13_32323232 (0x5 << 24)<br>
<br>
-#define XY_FAST_SRC_TRMODE_YF (1 << 31)<br>
-#define XY_FAST_DST_TRMODE_YF (1 << 30)<br>
-<br>
/* Pipeline Statistics Counter Registers */<br>
#define IA_VERTICES_COUNT 0x2310<br>
#define IA_PRIMITIVES_COUNT 0x2318<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c b/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
index 1cf6b04..83c1810 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
@@ -177,7 +177,7 @@ brw_get_depthstencil_tile_<wbr>masks(struct intel_mipmap_tree *depth_mt,<br>
uint32_t tile_mask_x = 0, tile_mask_y = 0;<br>
<br>
if (depth_mt) {<br>
- intel_get_tile_masks(depth_mt-<wbr>>tiling, depth_mt->tr_mode,<br>
+ intel_get_tile_masks(depth_mt-<wbr>>tiling,<br>
depth_mt->cpp,<br>
&tile_mask_x, &tile_mask_y);<br>
assert(!intel_miptree_level_<wbr>has_hiz(depth_mt, depth_level));<br>
@@ -194,7 +194,6 @@ brw_get_depthstencil_tile_<wbr>masks(struct intel_mipmap_tree *depth_mt,<br>
} else {<br>
uint32_t stencil_tile_mask_x, stencil_tile_mask_y;<br>
intel_get_tile_masks(stencil_<wbr>mt->tiling,<br>
- stencil_mt->tr_mode,<br>
stencil_mt->cpp,<br>
&stencil_tile_mask_x,<br>
&stencil_tile_mask_y);<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_tex_layout.c b/src/mesa/drivers/dri/i965/<wbr>brw_tex_layout.c<br>
index 8a528e0..bfa8afa 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_tex_layout.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_tex_layout.c<br>
@@ -40,74 +40,6 @@<br>
#define FILE_DEBUG_FLAG DEBUG_MIPTREE<br>
<br>
static unsigned int<br>
-tr_mode_horizontal_texture_<wbr>alignment(const struct intel_mipmap_tree *mt)<br>
-{<br>
- unsigned ret_align, divisor, multiplier_ys;<br>
-<br>
- /* Values in below tables specifiy the horizontal alignment requirement<br>
- * in elements for TRMODE_YF surface. An element is defined as a pixel in<br>
- * uncompressed surface formats, and as a compression block in compressed<br>
- * surface formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an<br>
- * element is a sample.<br>
- */<br>
- const unsigned align_1d_yf[] = {4096, 2048, 1024, 512, 256};<br>
- const unsigned align_2d_yf[] = {64, 64, 32, 32, 16};<br>
- const unsigned align_3d_yf[] = {16, 8, 8, 8, 4};<br>
-<br>
- assert(mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE);<br>
-<br>
- /* Alignment computations below assume a power of 2 cpp. */<br>
- assert (mt->cpp >= 1 && mt->cpp <= 16 && _mesa_is_pow_two(mt->cpp));<br>
- /* Compute array index. */<br>
- const int i = ffs(mt->cpp) - 1;<br>
-<br>
- switch(mt->target) {<br>
- case GL_TEXTURE_1D:<br>
- case GL_TEXTURE_1D_ARRAY:<br>
- ret_align = align_1d_yf[i];<br>
- multiplier_ys = 16;<br>
- break;<br>
- case GL_TEXTURE_2D:<br>
- case GL_TEXTURE_RECTANGLE:<br>
- case GL_TEXTURE_2D_ARRAY:<br>
- case GL_TEXTURE_CUBE_MAP:<br>
- case GL_TEXTURE_CUBE_MAP_ARRAY:<br>
- case GL_TEXTURE_2D_MULTISAMPLE:<br>
- case GL_TEXTURE_2D_MULTISAMPLE_<wbr>ARRAY:<br>
- ret_align = align_2d_yf[i];<br>
- multiplier_ys = 4;<br>
- break;<br>
- case GL_TEXTURE_3D:<br>
- ret_align = align_3d_yf[i];<br>
- multiplier_ys = 4;<br>
- break;<br>
- default:<br>
- unreachable("not reached");<br>
- }<br>
-<br>
- if (mt->tr_mode == INTEL_MIPTREE_TRMODE_YS)<br>
- ret_align *= multiplier_ys;<br>
-<br>
- assert(_mesa_is_pow_two(mt-><wbr>num_samples));<br>
-<br>
- switch (mt->num_samples) {<br>
- case 2:<br>
- case 4:<br>
- divisor = 2;<br>
- break;<br>
- case 8:<br>
- case 16:<br>
- divisor = 4;<br>
- break;<br>
- default:<br>
- divisor = 1;<br>
- break;<br>
- }<br>
- return ret_align / divisor;<br>
-}<br>
-<br>
-<br>
-static unsigned int<br>
intel_horizontal_texture_<wbr>alignment_unit(struct brw_context *brw,<br>
struct intel_mipmap_tree *mt,<br>
uint32_t layout_flags)<br>
@@ -141,63 +73,6 @@ intel_horizontal_texture_<wbr>alignment_unit(struct brw_context *brw,<br>
}<br>
<br>
static unsigned int<br>
-tr_mode_vertical_texture_<wbr>alignment(const struct intel_mipmap_tree *mt)<br>
-{<br>
- unsigned ret_align, divisor, multiplier_ys;<br>
-<br>
- /* Vertical alignment tables for TRMODE_YF */<br>
- const unsigned align_2d_yf[] = {64, 32, 32, 16, 16};<br>
- const unsigned align_3d_yf[] = {16, 16, 16, 8, 8};<br>
-<br>
- assert(mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE);<br>
-<br>
- /* Alignment computations below assume a power of 2 cpp. */<br>
- assert (mt->cpp >= 1 && mt->cpp <= 16 && _mesa_is_pow_two(mt->cpp)) ;<br>
- /* Compute array index. */<br>
- const int i = ffs(mt->cpp) - 1;<br>
-<br>
- switch(mt->target) {<br>
- case GL_TEXTURE_2D:<br>
- case GL_TEXTURE_RECTANGLE:<br>
- case GL_TEXTURE_2D_ARRAY:<br>
- case GL_TEXTURE_CUBE_MAP:<br>
- case GL_TEXTURE_CUBE_MAP_ARRAY:<br>
- case GL_TEXTURE_2D_MULTISAMPLE:<br>
- case GL_TEXTURE_2D_MULTISAMPLE_<wbr>ARRAY:<br>
- ret_align = align_2d_yf[i];<br>
- multiplier_ys = 4;<br>
- break;<br>
- case GL_TEXTURE_3D:<br>
- ret_align = align_3d_yf[i];<br>
- multiplier_ys = 2;<br>
- break;<br>
- case GL_TEXTURE_1D:<br>
- case GL_TEXTURE_1D_ARRAY:<br>
- default:<br>
- unreachable("Unexpected miptree target");<br>
- }<br>
-<br>
- if (mt->tr_mode == INTEL_MIPTREE_TRMODE_YS)<br>
- ret_align *= multiplier_ys;<br>
-<br>
- assert(_mesa_is_pow_two(mt-><wbr>num_samples));<br>
-<br>
- switch (mt->num_samples) {<br>
- case 4:<br>
- case 8:<br>
- divisor = 2;<br>
- break;<br>
- case 16:<br>
- divisor = 4;<br>
- break;<br>
- default:<br>
- divisor = 1;<br>
- break;<br>
- }<br>
- return ret_align / divisor;<br>
-}<br>
-<br>
-static unsigned int<br>
intel_vertical_texture_<wbr>alignment_unit(struct brw_context *brw,<br>
const struct intel_mipmap_tree *mt)<br>
{<br>
@@ -753,9 +628,6 @@ intel_miptree_set_alignment(<wbr>struct brw_context *brw,<br>
} else if (mt->format == MESA_FORMAT_S_UINT8) {<br>
mt->halign = 8;<br>
mt->valign = brw->gen >= 7 ? 8 : 4;<br>
- } else if (brw->gen >= 9 && mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) {<br>
- mt->halign = tr_mode_horizontal_texture_<wbr>alignment(mt);<br>
- mt->valign = tr_mode_vertical_texture_<wbr>alignment(mt);<br>
} else {<br>
mt->halign =<br>
intel_horizontal_texture_<wbr>alignment_unit(brw, mt, layout_flags);<br>
@@ -768,8 +640,6 @@ brw_miptree_layout(struct brw_context *brw,<br>
struct intel_mipmap_tree *mt,<br>
uint32_t layout_flags)<br>
{<br>
- mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE;<br>
-<br>
intel_miptree_set_alignment(<wbr>brw, mt, layout_flags);<br>
intel_miptree_set_total_width_<wbr>height(brw, mt);<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c<br>
index 3295175..467ada5 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c<br>
@@ -576,34 +576,6 @@ intel_lower_compressed_format(<wbr>struct brw_context *brw, mesa_format format)<br>
}<br>
}<br>
<br>
-/* This function computes Yf/Ys tiled bo size, alignment and pitch. */<br>
-static unsigned long<br>
-intel_get_yf_ys_bo_size(<wbr>struct intel_mipmap_tree *mt, unsigned *alignment,<br>
- unsigned long *pitch)<br>
-{<br>
- uint32_t tile_width, tile_height;<br>
- unsigned long stride, size, aligned_y;<br>
-<br>
- assert(mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE);<br>
- intel_get_tile_dims(mt-><wbr>tiling, mt->tr_mode, mt->cpp,<br>
- &tile_width, &tile_height);<br>
-<br>
- aligned_y = ALIGN(mt->total_height, tile_height);<br>
- stride = mt->total_width * mt->cpp;<br>
- stride = ALIGN(stride, tile_width);<br>
- size = stride * aligned_y;<br>
-<br>
- if (mt->tr_mode == INTEL_MIPTREE_TRMODE_YF) {<br>
- assert(size % 4096 == 0);<br>
- *alignment = 4096;<br>
- } else {<br>
- assert(size % (64 * 1024) == 0);<br>
- *alignment = 64 * 1024;<br>
- }<br>
- *pitch = stride;<br>
- return size;<br>
-}<br>
-<br>
static struct intel_mipmap_tree *<br>
miptree_create(struct brw_context *brw,<br>
GLenum target,<br>
@@ -642,27 +614,18 @@ miptree_create(struct brw_context *brw,<br>
unsigned long pitch;<br>
mt->etc_format = etc_format;<br>
<br>
- if (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) {<br>
- unsigned alignment = 0;<br>
- unsigned long size;<br>
- size = intel_get_yf_ys_bo_size(mt, &alignment, &pitch);<br>
- assert(size);<br>
- mt->bo = drm_intel_bo_alloc_for_render(<wbr>brw->bufmgr, "miptree",<br>
- size, alignment);<br>
+ if (format == MESA_FORMAT_S_UINT8) {<br>
+ /* Align to size of W tile, 64x64. */<br>
+ mt->bo = drm_intel_bo_alloc_tiled(brw-><wbr>bufmgr, "miptree",<br>
+ ALIGN(mt->total_width, 64),<br>
+ ALIGN(mt->total_height, 64),<br>
+ mt->cpp, &mt->tiling, &pitch,<br>
+ alloc_flags);<br>
} else {<br>
- if (format == MESA_FORMAT_S_UINT8) {<br>
- /* Align to size of W tile, 64x64. */<br>
- mt->bo = drm_intel_bo_alloc_tiled(brw-><wbr>bufmgr, "miptree",<br>
- ALIGN(mt->total_width, 64),<br>
- ALIGN(mt->total_height, 64),<br>
- mt->cpp, &mt->tiling, &pitch,<br>
- alloc_flags);<br>
- } else {<br>
- mt->bo = drm_intel_bo_alloc_tiled(brw-><wbr>bufmgr, "miptree",<br>
- mt->total_width, mt->total_height,<br>
- mt->cpp, &mt->tiling, &pitch,<br>
- alloc_flags);<br>
- }<br>
+ mt->bo = drm_intel_bo_alloc_tiled(brw-><wbr>bufmgr, "miptree",<br>
+ mt->total_width, mt->total_height,<br>
+ mt->cpp, &mt->tiling, &pitch,<br>
+ alloc_flags);<br>
}<br>
<br>
mt->pitch = pitch;<br>
@@ -1148,53 +1111,24 @@ intel_miptree_get_image_<wbr>offset(const struct intel_mipmap_tree *mt,<br>
* and tile_h is set to 1.<br>
*/<br>
void<br>
-intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,<br>
+intel_get_tile_dims(uint32_t tiling, uint32_t cpp,<br>
uint32_t *tile_w, uint32_t *tile_h)<br>
{<br>
- if (tr_mode == INTEL_MIPTREE_TRMODE_NONE) {<br>
- switch (tiling) {<br>
- case I915_TILING_X:<br>
- *tile_w = 512;<br>
- *tile_h = 8;<br>
- break;<br>
- case I915_TILING_Y:<br>
- *tile_w = 128;<br>
- *tile_h = 32;<br>
- break;<br>
- case I915_TILING_NONE:<br>
- *tile_w = cpp;<br>
- *tile_h = 1;<br>
- break;<br>
- default:<br>
- unreachable("not reached");<br>
- }<br>
- } else {<br>
- uint32_t aspect_ratio = 1;<br>
- assert(_mesa_is_pow_two(cpp));<br>
-<br>
- switch (cpp) {<br>
- case 1:<br>
- *tile_h = 64;<br>
- break;<br>
- case 2:<br>
- case 4:<br>
- *tile_h = 32;<br>
- break;<br>
- case 8:<br>
- case 16:<br>
- *tile_h = 16;<br>
- break;<br>
- default:<br>
- unreachable("not reached");<br>
- }<br>
-<br>
- if (cpp == 2 || cpp == 8)<br>
- aspect_ratio = 2;<br>
-<br>
- if (tr_mode == INTEL_MIPTREE_TRMODE_YS)<br>
- *tile_h *= 4;<br>
-<br>
- *tile_w = *tile_h * aspect_ratio * cpp;<br>
+ switch (tiling) {<br>
+ case I915_TILING_X:<br>
+ *tile_w = 512;<br>
+ *tile_h = 8;<br>
+ break;<br>
+ case I915_TILING_Y:<br>
+ *tile_w = 128;<br>
+ *tile_h = 32;<br>
+ break;<br>
+ case I915_TILING_NONE:<br>
+ *tile_w = cpp;<br>
+ *tile_h = 1;<br>
+ break;<br>
+ default:<br>
+ unreachable("not reached");<br>
}<br>
}<br>
<br>
@@ -1205,12 +1139,12 @@ intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,<br>
* untiled, the masks are set to 0.<br>
*/<br>
void<br>
-intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,<br>
+intel_get_tile_masks(uint32_t tiling, uint32_t cpp,<br>
uint32_t *mask_x, uint32_t *mask_y)<br>
{<br>
uint32_t tile_w_bytes, tile_h;<br>
<br>
- intel_get_tile_dims(tiling, tr_mode, cpp, &tile_w_bytes, &tile_h);<br>
+ intel_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h);<br>
<br>
*mask_x = tile_w_bytes / cpp - 1;<br>
*mask_y = tile_h - 1;<br>
@@ -1264,7 +1198,7 @@ intel_miptree_get_tile_<wbr>offsets(const struct intel_mipmap_tree *mt,<br>
uint32_t x, y;<br>
uint32_t mask_x, mask_y;<br>
<br>
- intel_get_tile_masks(mt-><wbr>tiling, mt->tr_mode, mt->cpp, &mask_x, &mask_y);<br>
+ intel_get_tile_masks(mt-><wbr>tiling, mt->cpp, &mask_x, &mask_y);<br>
intel_miptree_get_image_<wbr>offset(mt, level, slice, &x, &y);<br>
<br>
*tile_x = x & mask_x;<br>
@@ -3072,11 +3006,9 @@ use_intel_mipree_map_blit(<wbr>struct brw_context *brw,<br>
{<br>
if (brw->has_llc &&<br>
/* It's probably not worth swapping to the blit ring because of<br>
- * all the overhead involved. But, we must use blitter for the<br>
- * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.<br>
+ * all the overhead involved.<br>
*/<br>
- (!(mode & GL_MAP_WRITE_BIT) ||<br>
- mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) &&<br>
+ !(mode & GL_MAP_WRITE_BIT) &&<br>
!mt->compressed &&<br>
(mt->tiling == I915_TILING_X ||<br>
/* Prior to Sandybridge, the blitter can't handle Y tiling */<br>
@@ -3151,8 +3083,6 @@ intel_miptree_map(struct brw_context *brw,<br>
intel_miptree_map_movntdqa(<wbr>brw, mt, map, level, slice);<br>
#endif<br>
} else {<br>
- /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */<br>
- assert(mt->tr_mode == INTEL_MIPTREE_TRMODE_NONE);<br>
intel_miptree_map_gtt(brw, mt, map, level, slice);<br>
}<br>
<br>
@@ -3267,16 +3197,7 @@ intel_miptree_get_isl_tiling(<wbr>const struct intel_mipmap_tree *mt)<br>
case I915_TILING_X:<br>
return ISL_TILING_X;<br>
case I915_TILING_Y:<br>
- switch (mt->tr_mode) {<br>
- case INTEL_MIPTREE_TRMODE_NONE:<br>
return ISL_TILING_Y0;<br>
- case INTEL_MIPTREE_TRMODE_YF:<br>
- return ISL_TILING_Yf;<br>
- case INTEL_MIPTREE_TRMODE_YS:<br>
- return ISL_TILING_Ys;<br>
- default:<br>
- unreachable("Invalid tiled resource mode");<br>
- }<br>
default:<br>
unreachable("Invalid tiling mode");<br>
}<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.h<br>
index 27bcdfb..c03233a 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.h<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.h<br>
@@ -333,13 +333,6 @@ struct intel_miptree_hiz_buffer<br>
struct intel_mipmap_tree *mt;<br>
};<br>
<br>
-/* Tile resource modes */<br>
-enum intel_miptree_tr_mode {<br>
- INTEL_MIPTREE_TRMODE_NONE,<br>
- INTEL_MIPTREE_TRMODE_YF,<br>
- INTEL_MIPTREE_TRMODE_YS<br>
-};<br>
-<br>
struct intel_mipmap_tree<br>
{<br>
/**<br>
@@ -374,12 +367,6 @@ struct intel_mipmap_tree<br>
uint32_t tiling;<br>
<br>
/**<br>
- * @see RENDER_SURFACE_STATE.<wbr>TiledResourceMode<br>
- * @see 3DSTATE_DEPTH_BUFFER.<wbr>TiledResourceMode<br>
- */<br>
- enum intel_miptree_tr_mode tr_mode;<br>
-<br>
- /**<br>
* @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.<br>
*<br>
* @see RENDER_SURFACE_STATE.<wbr>SurfaceType<br>
@@ -806,11 +793,11 @@ intel_get_image_dims(struct gl_texture_image *image,<br>
int *width, int *height, int *depth);<br>
<br>
void<br>
-intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,<br>
+intel_get_tile_masks(uint32_t tiling, uint32_t cpp,<br>
uint32_t *mask_x, uint32_t *mask_y);<br>
<br>
void<br>
-intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,<br>
+intel_get_tile_dims(uint32_t tiling, uint32_t cpp,<br>
uint32_t *tile_w, uint32_t *tile_h);<br>
<br>
uint32_t<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.9.3<br>
<br>
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