<div dir="ltr">Two people have independently pointed out the i916 typo. I've fixed it locally. </div><div class="gmail_extra"> <div class="gmail_quote">On Fri, Mar 31, 2017 at 4:17 PM, Jason Ekstrand <<a href="mailto:jason@jlekstrand.net" target="_blank">jason@jlekstrand.net</a>> wrote: <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Cc: "13.0 17.0" <<a href="mailto:mesa-stable@lists.freedesktop.org">mesa-stable@lists.freedesktop.org</a>> --- src/mesa/drivers/dri/i965/genX_blorp_exec.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c index f9334ee..b6122a3 100644 --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c @@ -122,8 +122,19 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size, assert(batch->blorp->driver_ctx == batch->driver_batch); struct brw_context *brw = batch->driver_batch; + /* From the Sky Lake PRM, 3DSTATE_VERTEX_BUFFERS: + * + * "The VF cache needs to be invalidated before binding and then using + * Vertex Buffers that overlap with any previously bound Vertex Buffer + * (at a 64B granularity) since the last invalidation. A VF cache + * invalidate is performed by setting the "VF Cache Invalidation Enable" + * bit in PIPE_CONTROL." + * + * In order to avoid this problem, we align all vertex buffer allocations + * to 64 bytes. + */ uint32_t offset; - void *data = brw_state_batch(brw, size, 32, &offset); + void *data = brw_state_batch(brw, size, 64, &offset); *addr = (struct blorp_address) { .buffer = brw-><a href="http://batch.bo" rel="noreferrer" target="_blank">batch.bo</a>, -- 2.5.0.400.gff86faf </blockquote></div> </div>