<div dir="ltr"><div>Fixes: ec15e0d30 "radv: optimise compute shader grid size emission."<br></div>Tested-by: Grazvydas Ignotas <<a href="mailto:notasas@gmail.com">notasas@gmail.com</a>><br> <div class="gmail_extra"><div class="gmail_quote">On Sat, Apr 22, 2017 at 7:42 PM, Bas Nieuwenhuizen <span dir="ltr"><<a href="mailto:bas@basnieuwenhuizen.nl" target="_blank">bas@basnieuwenhuizen.nl</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Signed-off-by: Bas Nieuwenhuizen <<a href="mailto:basni@google.com">basni@google.com</a>><br>
---<br>
src/amd/vulkan/radv_cmd_<wbr>buffer.c | 6 +++---<br>
1 file changed, 3 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/src/amd/vulkan/radv_cmd_<wbr>buffer.c b/src/amd/vulkan/radv_cmd_<wbr>buffer.c<br>
index 958ae6e361e..ffa7e430b2b 100644<br>
--- a/src/amd/vulkan/radv_cmd_<wbr>buffer.c<br>
+++ b/src/amd/vulkan/radv_cmd_<wbr>buffer.c<br>
@@ -2842,7 +2842,7 @@ void radv_CmdDispatch(<br>
MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);<br>
if (loc->sgpr_idx != -1) {<br>
assert(!loc->indirect);<br>
- uint8_t grid_used = cmd_buffer->state.pipeline-><wbr>shaders[MESA_SHADER_COMPUTE]-><wbr>info.info.cs.grid_components_<wbr>used;<br>
+ uint8_t grid_used = cmd_buffer->state.compute_<wbr>pipeline->shaders[MESA_SHADER_<wbr>COMPUTE]->info.info.cs.grid_<wbr>components_used;<br>
assert(loc->num_sgprs == grid_used);<br>
radeon_set_sh_reg_seq(cmd_<wbr>buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);<br>
radeon_emit(cmd_buffer->cs, x);<br>
@@ -2881,7 +2881,7 @@ void radv_CmdDispatchIndirect(<br>
struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_<wbr>buffer->state.compute_<wbr>pipeline,<br>
MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);<br>
if (loc->sgpr_idx != -1) {<br>
- uint8_t grid_used = cmd_buffer->state.pipeline-><wbr>shaders[MESA_SHADER_COMPUTE]-><wbr>info.info.cs.grid_components_<wbr>used;<br>
+ uint8_t grid_used = cmd_buffer->state.compute_<wbr>pipeline->shaders[MESA_SHADER_<wbr>COMPUTE]->info.info.cs.grid_<wbr>components_used;<br>
for (unsigned i = 0; i < grid_used; ++i) {<br>
radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));<br>
radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_<wbr>MEM) |<br>
@@ -2953,7 +2953,7 @@ void radv_unaligned_dispatch(<br>
struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_<wbr>buffer->state.compute_<wbr>pipeline,<br>
MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);<br>
if (loc->sgpr_idx != -1) {<br>
- uint8_t grid_used = cmd_buffer->state.pipeline-><wbr>shaders[MESA_SHADER_COMPUTE]-><wbr>info.info.cs.grid_components_<wbr>used;<br>
+ uint8_t grid_used = cmd_buffer->state.compute_<wbr>pipeline->shaders[MESA_SHADER_<wbr>COMPUTE]->info.info.cs.grid_<wbr>components_used;<br>
radeon_set_sh_reg_seq(cmd_<wbr>buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);<br>
radeon_emit(cmd_buffer->cs, blocks[0]);<br>
if (grid_used > 1)<br>
<span class="gmail-HOEnZb"><font color="#888888">--<br>
2.12.2<br>
<br>
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</font></span></blockquote></div><br></div></div>