<div dir="ltr"><div><div><div><div>I *think* most of this patch goes away if we have a new ISL_DIM_LAYOUT_GEN6_BACK_TO_BACK because we won't be pushing the isl_dev in everywhere. </div>That said, it'd be nice if you would split out the bit which adds the isl_surf with a commit message something like this: </div>i965: Add an isl_surf to intel_mipmap_tree </div>This new struct field is initialized to zero when the intel_mipmap_tree struct is allocated so users of intel_mipmap_tree can easily know whether or not the mt->surf struct contains valid data by checking intel_mipmap_tree::surf > 0. </div>--Jason <div><div><div><div><div><div class="gmail_extra"> <div class="gmail_quote">On Wed, May 3, 2017 at 2:22 AM, Topi Pohjolainen <<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>> wrote: <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>> --- src/mesa/drivers/dri/i965/brw_misc_state.c | 12 +-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 11 ++- src/mesa/drivers/dri/i965/intel_blit.c | 8 +- src/mesa/drivers/dri/i965/intel_fbo.c | 9 +- src/mesa/drivers/dri/i965/intel_fbo.h | 9 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 102 +++++++++++++++++------ src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 8 +- src/mesa/drivers/dri/i965/intel_screen.c | 3 +- src/mesa/drivers/dri/i965/intel_tex_image.c | 2 +- 9 files changed, 115 insertions(+), 49 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 9dd6ab8..2911739 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -313,7 +313,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw, stencil_irb != depth_irb && stencil_irb->mt == depth_mt) { intel_miptree_reference(&stencil_irb->mt, depth_irb->mt); - intel_renderbuffer_set_draw_offset(stencil_irb); + intel_renderbuffer_set_draw_offset(&brw->isl_dev, stencil_irb); } stencil_mt = get_stencil_miptree(stencil_irb); @@ -324,7 +324,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw, if (stencil_irb) { stencil_mt = get_stencil_miptree(stencil_irb); - intel_miptree_get_image_offset(stencil_mt, + intel_miptree_get_image_offset(&brw->isl_dev, stencil_mt, stencil_irb->mt_level, stencil_irb->mt_layer, &stencil_draw_x, &stencil_draw_y); @@ -345,7 +345,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw, /* If we have (just) stencil, check it for ignored low bits as well */ if (stencil_irb) { - intel_miptree_get_image_offset(stencil_mt, + intel_miptree_get_image_offset(&brw->isl_dev, stencil_mt, stencil_irb->mt_level, stencil_irb->mt_layer, &stencil_draw_x, &stencil_draw_y); @@ -369,7 +369,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw, intel_renderbuffer_move_to_temp(brw, stencil_irb, invalidate_stencil); stencil_mt = get_stencil_miptree(stencil_irb); - intel_miptree_get_image_offset(stencil_mt, + intel_miptree_get_image_offset(&brw->isl_dev, stencil_mt, stencil_irb->mt_level, stencil_irb->mt_layer, &stencil_draw_x, &stencil_draw_y); @@ -378,7 +378,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw, if (depth_irb && depth_irb->mt == stencil_irb->mt) { intel_miptree_reference(&depth_irb->mt, stencil_irb->mt); - intel_renderbuffer_set_draw_offset(depth_irb); + intel_renderbuffer_set_draw_offset(&brw->isl_dev, depth_irb); } else if (depth_irb && !rebase_depth) { if (tile_x != stencil_tile_x || tile_y != stencil_tile_y) { @@ -397,7 +397,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw, if (stencil_irb && stencil_irb->mt == depth_mt) { intel_miptree_reference(&stencil_irb->mt, depth_irb->mt); - intel_renderbuffer_set_draw_offset(stencil_irb); + intel_renderbuffer_set_draw_offset(&brw->isl_dev, stencil_irb); } WARN_ONCE(stencil_tile_x != tile_x || diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index b2eca07..b3d9382 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -105,7 +105,8 @@ brw_emit_surface_state(struct brw_context *brw, assert(view.levels == 1 && view.array_len == 1); assert(tile_x == 0 && tile_y == 0); - offset += intel_miptree_get_tile_offsets(mt, view.base_level, + offset += intel_miptree_get_tile_offsets(&brw->isl_dev, mt, + view.base_level, view.base_array_layer, &tile_x, &tile_y); @@ -999,7 +1000,8 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, assert(!(flags & INTEL_AUX_BUFFER_DISABLED)); if (rb->TexImage && !brw->has_surface_tile_offset) { - intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y); + intel_renderbuffer_get_tile_offsets(&brw->isl_dev, irb, + &tile_x, &tile_y); if (tile_x != 0 || tile_y != 0) { /* Original gen4 hardware couldn't draw to a non-tile-aligned @@ -1026,7 +1028,8 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, /* reloc */ assert(mt->offset % mt->cpp == 0); - surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) + + surf[1] = (intel_renderbuffer_get_tile_offsets(&brw->isl_dev, irb, + &tile_x, &tile_y) + mt->bo->offset64 + mt->offset); surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT | @@ -1655,7 +1658,7 @@ update_texture_image_param(struct brw_context *brw, minify(mt->logical_depth0, u->Level) : mt->logical_depth0); - intel_miptree_get_image_offset(mt, u->Level, u->_Layer, + intel_miptree_get_image_offset(&brw->isl_dev, mt, u->Level, u->_Layer, &param->offset[0], &param->offset[1]); diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 568ed54..4cd86dd 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -337,9 +337,9 @@ intel_miptree_blit(struct brw_context *brw, dst_y = minify(dst_mt->physical_height0, dst_level - dst_mt->first_level) - dst_y - height; uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y; - intel_miptree_get_image_offset(src_mt, src_level, src_slice, + intel_miptree_get_image_offset(&brw->isl_dev, src_mt, src_level, src_slice, &src_image_x, &src_image_y); - intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice, + intel_miptree_get_image_offset(&brw->isl_dev, dst_mt, dst_level, dst_slice, &dst_image_x, &dst_image_y); src_x += src_image_x; src_y += src_image_y; @@ -389,7 +389,7 @@ intel_miptree_copy(struct brw_context *brw, intel_miptree_resolve_color(brw, dst_mt, dst_level, dst_slice, 1, 0); uint32_t src_image_x, src_image_y; - intel_miptree_get_image_offset(src_mt, src_level, src_slice, + intel_miptree_get_image_offset(&brw->isl_dev, src_mt, src_level, src_slice, &src_image_x, &src_image_y); if (_mesa_is_format_compressed(src_mt->format)) { @@ -418,7 +418,7 @@ intel_miptree_copy(struct brw_context *brw, src_y += src_image_y; uint32_t dst_image_x, dst_image_y; - intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice, + intel_miptree_get_image_offset(&brw->isl_dev, dst_mt, dst_level, dst_slice, &dst_image_x, &dst_image_y); if (_mesa_is_format_compressed(dst_mt->format)) { diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 21e8e86..27446cc 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -559,7 +559,7 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw, intel_miptree_reference(&irb->mt, mt); - intel_renderbuffer_set_draw_offset(irb); + intel_renderbuffer_set_draw_offset(&brw->isl_dev, irb); if (intel_miptree_wants_hiz_buffer(brw, mt)) { intel_miptree_alloc_hiz(brw, mt); @@ -571,12 +571,13 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw, } void -intel_renderbuffer_set_draw_offset(struct intel_renderbuffer *irb) +intel_renderbuffer_set_draw_offset(const struct isl_device *isl_dev, + struct intel_renderbuffer *irb) { unsigned int dst_x, dst_y; /* compute offset of the particular 2D image within the texture region */ - intel_miptree_get_image_offset(irb->mt, + intel_miptree_get_image_offset(isl_dev, irb->mt, irb->mt_level, irb->mt_layer, &dst_x, &dst_y); @@ -1043,7 +1044,7 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw, intel_miptree_copy_teximage(brw, intel_image, new_mt, invalidate); intel_miptree_reference(&irb->mt, intel_image->mt); - intel_renderbuffer_set_draw_offset(irb); + intel_renderbuffer_set_draw_offset(&brw->isl_dev, irb); intel_miptree_release(&new_mt); } diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h b/src/mesa/drivers/dri/i965/intel_fbo.h index 08b82e8..a9c4546 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.h +++ b/src/mesa/drivers/dri/i965/intel_fbo.h @@ -181,14 +181,17 @@ extern void intel_fbo_init(struct brw_context *brw); void -intel_renderbuffer_set_draw_offset(struct intel_renderbuffer *irb); +intel_renderbuffer_set_draw_offset(const struct isl_device *isl_dev, + struct intel_renderbuffer *irb); static inline uint32_t -intel_renderbuffer_get_tile_offsets(struct intel_renderbuffer *irb, +intel_renderbuffer_get_tile_offsets(const struct isl_device *isl_dev, + struct intel_renderbuffer *irb, uint32_t *tile_x, uint32_t *tile_y) { - return intel_miptree_get_tile_offsets(irb->mt, irb->mt_level, irb->mt_layer, + return intel_miptree_get_tile_offsets(isl_dev, irb->mt, + irb->mt_level, irb->mt_layer, tile_x, tile_y); } diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index d80a1b6..e91992c 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -1082,10 +1082,25 @@ intel_miptree_set_image_offset(struct intel_mipmap_tree *mt, } void -intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt, +intel_miptree_get_image_offset(const struct isl_device *isl_dev, + const struct intel_mipmap_tree *mt, GLuint level, GLuint slice, GLuint *x, GLuint *y) { + if (mt->surf.size > 0) { + uint32_t x_offset_sa, y_offset_sa; + const unsigned z = mt->surf.dim_layout == ISL_DIM_LAYOUT_GEN4_3D ? + slice : 0; + slice = mt->surf.dim_layout == ISL_DIM_LAYOUT_GEN4_3D ? + 0 : slice; + isl_surf_get_image_offset_sa(isl_dev, &mt->surf, level, slice, z, + &x_offset_sa, &y_offset_sa); + + *x = x_offset_sa; + *y = y_offset_sa; + return; + } + assert(slice < mt->level[level].depth); *x = mt->level[level].slice[slice].x_offset; @@ -1178,7 +1193,8 @@ intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt, * from there. */ uint32_t -intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt, +intel_miptree_get_tile_offsets(const struct isl_device *isl_dev, + const struct intel_mipmap_tree *mt, GLuint level, GLuint slice, uint32_t *tile_x, uint32_t *tile_y) @@ -1187,7 +1203,7 @@ intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt, uint32_t mask_x, mask_y; intel_get_tile_masks(mt->tiling, mt->cpp, &mask_x, &mask_y); - intel_miptree_get_image_offset(mt, level, slice, &x, &y); + intel_miptree_get_image_offset(isl_dev, mt, level, slice, &x, &y); *tile_x = x & mask_x; *tile_y = y & mask_y; @@ -1206,7 +1222,8 @@ intel_miptree_copy_slice_sw(struct brw_context *brw, { void *src, *dst; ptrdiff_t src_stride, dst_stride; - int cpp = dst_mt->cpp; + const int cpp = dst_mt->surf.size > 0 ? + (isl_format_get_layout(dst_mt->surf.format)->bpb / 8) : dst_mt->cpp; intel_miptree_map(brw, src_mt, level, slice, @@ -1299,8 +1316,10 @@ intel_miptree_copy_slice(struct brw_context *brw, } uint32_t dst_x, dst_y, src_x, src_y; - intel_miptree_get_image_offset(dst_mt, level, slice, &dst_x, &dst_y); - intel_miptree_get_image_offset(src_mt, level, slice, &src_x, &src_y); + intel_miptree_get_image_offset(&brw->isl_dev, + dst_mt, level, slice, &dst_x, &dst_y); + intel_miptree_get_image_offset(&brw->isl_dev, + src_mt, level, slice, &src_x, &src_y); DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n", _mesa_get_format_name(src_mt->format), @@ -2236,11 +2255,12 @@ intel_miptree_map_gtt(struct brw_context *brw, /* Note that in the case of cube maps, the caller must have passed the * slice number referencing the face. */ - intel_miptree_get_image_offset(mt, level, slice, &image_x, &image_y); + intel_miptree_get_image_offset(&brw->isl_dev, + mt, level, slice, &image_x, &image_y); x += image_x; y += image_y; - map->stride = mt->pitch; + map->stride = mt->surf.size > 0 ? mt->surf.row_pitch : mt->pitch; map->ptr = base + y * map->stride + x * mt->cpp; } @@ -2274,7 +2294,8 @@ intel_miptree_map_blit(struct brw_context *brw, fprintf(stderr, "Failed to allocate blit temporary\n"); goto fail; } - map->stride = map->linear_mt->pitch; + map->stride = map->linear_mt->surf.size > 0 ? + map->linear_mt->surf.row_pitch : map->linear_mt->pitch; /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless @@ -2349,7 +2370,8 @@ intel_miptree_map_movntdqa(struct brw_context *brw, /* Map the original image */ uint32_t image_x; uint32_t image_y; - intel_miptree_get_image_offset(mt, level, slice, &image_x, &image_y); + intel_miptree_get_image_offset(&brw->isl_dev, + mt, level, slice, &image_x, &image_y); image_x += map->x; image_y += map->y; @@ -2359,15 +2381,20 @@ intel_miptree_map_movntdqa(struct brw_context *brw, src += mt->offset; - src += image_y * mt->pitch; - src += image_x * mt->cpp; + if (mt->surf.size > 0) { + src += image_y * mt->surf.row_pitch; + src += image_x * (isl_format_get_layout(mt->surf.format)->bpb / 8); + } else { + src += image_y * mt->pitch; + src += image_x * mt->cpp; + } /* Due to the pixel offsets for the particular image being mapped, our * src pointer may not be 16-byte aligned. However, if the pitch is * divisible by 16, then the amount by which it's misaligned will remain * consistent from row to row. */ - assert((mt->pitch % 16) == 0); + assert(((mt->surf.size > 0 ? mt->surf.row_pitch : mt->pitch) % 16) == 0); const int misalignment = ((uintptr_t) src) & 15; /* Create an untiled temporary buffer for the mapping. */ @@ -2421,15 +2448,22 @@ intel_miptree_map_s8(struct brw_context *brw, * temporary buffer back out. */ if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) { + /* ISL uses a stencil pitch value that is expected by hardware whereas + * traditional miptree uses half of that. Below the value gets supplied + * to intel_offset_S8() which expects the legacy interpretation. + */ + const unsigned pitch = mt->surf.size > 0 ? + mt->surf.row_pitch / 2 : mt->pitch; uint8_t *untiled_s8_map = map->ptr; uint8_t *tiled_s8_map = intel_miptree_map_raw(brw, mt); unsigned int image_x, image_y; - intel_miptree_get_image_offset(mt, level, slice, &image_x, &image_y); + intel_miptree_get_image_offset(&brw->isl_dev, + mt, level, slice, &image_x, &image_y); for (uint32_t y = 0; y < map->h; y++) { for (uint32_t x = 0; x < map->w; x++) { - ptrdiff_t offset = intel_offset_S8(mt->pitch, + ptrdiff_t offset = intel_offset_S8(pitch, x + image_x + map->x, y + image_y + map->y, brw->has_swizzling); @@ -2457,15 +2491,22 @@ intel_miptree_unmap_s8(struct brw_context *brw, unsigned int slice) { if (map->mode & GL_MAP_WRITE_BIT) { + /* ISL uses a stencil pitch value that is expected by hardware whereas + * traditional miptree uses half of that. Below the value gets supplied + * to intel_offset_S8() which expects the legacy interpretation. + */ + const unsigned pitch = mt->surf.size > 0 ? + mt->surf.row_pitch / 2: mt->pitch; unsigned int image_x, image_y; uint8_t *untiled_s8_map = map->ptr; uint8_t *tiled_s8_map = intel_miptree_map_raw(brw, mt); - intel_miptree_get_image_offset(mt, level, slice, &image_x, &image_y); + intel_miptree_get_image_offset(&brw->isl_dev, + mt, level, slice, &image_x, &image_y); for (uint32_t y = 0; y < map->h; y++) { for (uint32_t x = 0; x < map->w; x++) { - ptrdiff_t offset = intel_offset_S8(mt->pitch, + ptrdiff_t offset = intel_offset_S8(pitch, image_x + x + map->x, image_y + y + map->y, brw->has_swizzling); @@ -2509,7 +2550,8 @@ intel_miptree_unmap_etc(struct brw_context *brw, { uint32_t image_x; uint32_t image_y; - intel_miptree_get_image_offset(mt, level, slice, &image_x, &image_y); + intel_miptree_get_image_offset(&brw->isl_dev, + mt, level, slice, &image_x, &image_y); image_x += map->x; image_y += map->y; @@ -2564,21 +2606,27 @@ intel_miptree_map_depthstencil(struct brw_context *brw, * temporary buffer back out. */ if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) { + /* ISL uses a stencil pitch value that is expected by hardware whereas + * traditional miptree uses half of that. Below the value gets supplied + * to intel_offset_S8() which expects the legacy interpretation. + */ + const unsigned s_pitch = s_mt->surf.size > 0 ? + s_mt->surf.row_pitch / 2 : s_mt->pitch; uint32_t *packed_map = map->ptr; uint8_t *s_map = intel_miptree_map_raw(brw, s_mt); uint32_t *z_map = intel_miptree_map_raw(brw, z_mt); unsigned int s_image_x, s_image_y; unsigned int z_image_x, z_image_y; - intel_miptree_get_image_offset(s_mt, level, slice, + intel_miptree_get_image_offset(&brw->isl_dev, s_mt, level, slice, &s_image_x, &s_image_y); - intel_miptree_get_image_offset(z_mt, level, slice, + intel_miptree_get_image_offset(&brw->isl_dev, z_mt, level, slice, &z_image_x, &z_image_y); for (uint32_t y = 0; y < map->h; y++) { for (uint32_t x = 0; x < map->w; x++) { int map_x = map->x + x, map_y = map->y + y; - ptrdiff_t s_offset = intel_offset_S8(s_mt->pitch, + ptrdiff_t s_offset = intel_offset_S8(s_pitch, map_x + s_image_x, map_y + s_image_y, brw->has_swizzling); @@ -2625,20 +2673,26 @@ intel_miptree_unmap_depthstencil(struct brw_context *brw, bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z_FLOAT32; if (map->mode & GL_MAP_WRITE_BIT) { + /* ISL uses a stencil pitch value that is expected by hardware whereas + * traditional miptree uses half of that. Below the value gets supplied + * to intel_offset_S8() which expects the legacy interpretation. + */ + const unsigned s_pitch = s_mt->surf.size > 0 ? + s_mt->surf.row_pitch / 2 : s_mt->pitch; uint32_t *packed_map = map->ptr; uint8_t *s_map = intel_miptree_map_raw(brw, s_mt); uint32_t *z_map = intel_miptree_map_raw(brw, z_mt); unsigned int s_image_x, s_image_y; unsigned int z_image_x, z_image_y; - intel_miptree_get_image_offset(s_mt, level, slice, + intel_miptree_get_image_offset(&brw->isl_dev, s_mt, level, slice, &s_image_x, &s_image_y); - intel_miptree_get_image_offset(z_mt, level, slice, + intel_miptree_get_image_offset(&brw->isl_dev, z_mt, level, slice, &z_image_x, &z_image_y); for (uint32_t y = 0; y < map->h; y++) { for (uint32_t x = 0; x < map->w; x++) { - ptrdiff_t s_offset = intel_offset_S8(s_mt->pitch, + ptrdiff_t s_offset = intel_offset_S8(s_pitch, x + s_image_x + map->x, y + s_image_y + map->y, brw->has_swizzling); diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 913fb4c..672b5f4 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -323,6 +323,8 @@ struct intel_miptree_aux_buffer struct intel_mipmap_tree { + struct isl_surf surf; + /** * Buffer object containing the surface. * @@ -748,7 +750,8 @@ bool intel_miptree_match_image(struct intel_mipmap_tree *mt, struct gl_texture_image *image); void -intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt, +intel_miptree_get_image_offset(const struct isl_device *isl_dev, + const struct intel_mipmap_tree *mt, GLuint level, GLuint slice, GLuint *x, GLuint *y); @@ -788,7 +791,8 @@ intel_get_tile_dims(uint32_t tiling, uint32_t cpp, uint32_t *tile_w, uint32_t *tile_h); uint32_t -intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt, +intel_miptree_get_tile_offsets(const struct isl_device *isl_dev, + const struct intel_mipmap_tree *mt, GLuint level, GLuint slice, uint32_t *tile_x, uint32_t *tile_y); diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 34a5f18..c08192a 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -371,7 +371,8 @@ intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image, image->height = minify(mt->physical_height0, level - mt->first_level); image->pitch = mt->pitch; - image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset, + image->offset = intel_miptree_get_tile_offsets(&brw->isl_dev, + mt, level, zoffset, &image->tile_x, &image->tile_y); diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index 7208d8e..9aa2f70 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c @@ -272,7 +272,7 @@ create_mt_for_dri_image(struct brw_context *brw, mt->level[0].slice[0].x_offset = image->tile_x; mt->level[0].slice[0].y_offset = image->tile_y; - intel_miptree_get_tile_offsets(mt, 0, 0, &draw_x, &draw_y); + intel_miptree_get_tile_offsets(&brw->isl_dev, mt, 0, 0, &draw_x, &draw_y); /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has -- 2.9.3 _______________________________________________ mesa-dev mailing list <a href="mailto:mesa-dev@lists.freedesktop.org">mesa-dev@lists.freedesktop.org</a> <a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev" rel="noreferrer" target="_blank">https://lists.freedesktop.org/mailman/listinfo/mesa-dev</a> </blockquote></div> </div></div></div></div></div></div></div>