<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Wed, May 3, 2017 at 2:22 AM, Topi Pohjolainen <span dir="ltr"><<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>><br>
---<br>
src/mesa/drivers/dri/i965/<wbr>intel_blit.c | 37 +++++++++++++++++++++++++-----<wbr>----<br>
src/mesa/drivers/dri/i965/<wbr>intel_blit.h | 13 ++++++++++++<br>
2 files changed, 41 insertions(+), 9 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>intel_blit.c b/src/mesa/drivers/dri/i965/<wbr>intel_blit.c<br>
index 4cd86dd..be6a851 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>intel_blit.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>intel_blit.c<br>
@@ -131,6 +131,10 @@ set_blitter_tiling(struct brw_context *brw,<br>
static int<br>
blt_pitch(struct intel_mipmap_tree *mt)<br>
{<br>
+ if (mt->surf.size > 0)<br>
+ return (mt->surf.tiling != ISL_TILING_LINEAR) ?<br>
+ mt->surf.row_pitch / 4 : mt->surf.row_pitch;<br>
+<br>
int pitch = mt->pitch;<br>
if (mt->tiling)<br>
pitch /= 4;<br>
@@ -171,9 +175,13 @@ get_blit_intratile_offset_el(<wbr>const struct brw_context *brw,<br>
uint32_t *x_offset_el,<br>
uint32_t *y_offset_el)<br>
{<br>
+ const unsigned cpp = mt->surf.size > 0 ?<br>
+ isl_format_get_layout(mt-><wbr>surf.format)->bpb / 8 : mt->cpp;<br>
+ const unsigned pitch = mt->surf.size > 0 ? mt->surf.row_pitch : mt->pitch;<br>
+<br>
enum isl_tiling tiling = intel_miptree_get_isl_tiling(<wbr>mt);<br>
isl_tiling_get_intratile_<wbr>offset_el(&brw->isl_dev,<br>
- tiling, mt->cpp, mt->pitch,<br>
+ tiling, cpp, pitch,<br>
total_x_offset_el, total_y_offset_el,<br>
base_address_offset,<br>
x_offset_el, y_offset_el);<br>
@@ -188,11 +196,11 @@ get_blit_intratile_offset_el(<wbr>const struct brw_context *brw,<br>
* The offsets we get from ISL in the tiled case are already aligned.<br>
* In the linear case, we need to do some of our own aligning.<br>
*/<br>
- assert(mt->pitch % 64 == 0);<br>
+ assert(pitch % 64 == 0);<br>
uint32_t delta = *base_address_offset & 63;<br>
- assert(delta % mt->cpp == 0);<br>
+ assert(delta % cpp == 0);<br>
*base_address_offset -= delta;<br>
- *x_offset_el += delta / mt->cpp;<br>
+ *x_offset_el += delta / cpp;<br>
} else {<br>
assert(*base_address_offset % 4096 == 0);<br>
}<br>
@@ -207,6 +215,17 @@ emit_miptree_blit(struct brw_context *brw,<br>
uint32_t width, uint32_t height,<br>
bool reverse, GLenum logicop)<br>
{<br>
+ const unsigned src_cpp = src_mt->surf.size > 0 ?<br>
+ isl_format_get_layout(src_mt-><wbr>surf.format)->bpb / 8 : src_mt->cpp;<br>
+ const unsigned src_pitch =<br>
+ src_mt->surf.size > 0 ? src_mt->surf.row_pitch : src_mt->pitch;<br>
+ const unsigned dst_pitch =<br>
+ dst_mt->surf.size > 0 ? dst_mt->surf.row_pitch : dst_mt->pitch;<br>
+ const unsigned src_tiling = src_mt->surf.size > 0 ?<br>
+ isl_tiling_to_bufmgr_tiling(<wbr>src_mt->surf.tiling) : src_mt->tiling;<br>
+ const unsigned dst_tiling = dst_mt->surf.size > 0 ?<br>
+ isl_tiling_to_bufmgr_tiling(<wbr>dst_mt->surf.tiling) : dst_mt->tiling;<br></blockquote><div><br></div><div>I know you really like const but... This would probably be easier to read as an if-else than as 5 ternaries.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+<br>
/* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics<br>
* Data Size Limitations):<br>
*<br>
@@ -251,13 +270,13 @@ emit_miptree_blit(struct brw_context *brw,<br>
&dst_offset, &dst_tile_x, &dst_tile_y);<br>
<br>
if (!intelEmitCopyBlit(brw,<br>
- src_mt->cpp,<br>
- reverse ? -src_mt->pitch : src_mt->pitch,<br>
+ src_cpp,<br>
+ reverse ? -src_pitch : src_pitch,<br>
src_mt->bo, src_mt->offset + src_offset,<br>
- src_mt->tiling,<br>
- dst_mt->pitch,<br>
+ src_tiling,<br>
+ dst_pitch,<br>
dst_mt->bo, dst_mt->offset + dst_offset,<br>
- dst_mt->tiling,<br>
+ dst_tiling,<br>
src_tile_x, src_tile_y,<br>
dst_tile_x, dst_tile_y,<br>
chunk_w, chunk_h,<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>intel_blit.h b/src/mesa/drivers/dri/i965/<wbr>intel_blit.h<br>
index 2604417..5e4d1f5 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>intel_blit.h<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>intel_blit.h<br>
@@ -28,6 +28,19 @@<br>
<br>
#include "brw_context.h"<br>
<br>
+static inline unsigned<br>
+isl_tiling_to_bufmgr_tiling(<wbr>enum isl_tiling tiling)<br>
+{<br>
+ if (tiling == ISL_TILING_X)<br>
+ return I915_TILING_X;<br>
+<br>
+ if (tiling == ISL_TILING_Y0)<br>
+ return I915_TILING_Y;<br>
+<br>
+ /* All other are unknown to buffer allocator. */<br>
+ return I915_TILING_NONE;<br>
+}<br>
+<br>
bool<br>
intelEmitCopyBlit(struct brw_context *brw,<br>
GLuint cpp,<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.9.3<br>
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