<div dir="auto"><div>Hi Marek,</div><div dir="auto"><br></div><div dir="auto">A comment below</div><div dir="auto"><div class="gmail_extra" dir="auto"><br><div class="gmail_quote">Den 10 maj 2017 20:29 skrev "Marek Olšák" <<a href="mailto:maraeo@gmail.com">maraeo@gmail.com</a>>:<br type="attribution"><blockquote class="quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Marek Olšák <<a href="mailto:marek.olsak@amd.com">marek.olsak@amd.com</a>><br>
<br>
Cc: 17.1 <<a href="mailto:mesa-stable@lists.freedesktop.org">mesa-stable@lists.<wbr>freedesktop.org</a>><br>
Reviewed-by: Alex Deucher <<a href="mailto:alexander.deucher@amd.com">alexander.deucher@amd.com</a>><br>
Reviewed-by: Nicolai Hähnle <<a href="mailto:nicolai.haehnle@amd.com">nicolai.haehnle@amd.com</a>><br>
---<br>
src/amd/addrlib/gfx9/<wbr>gfx9addrlib.cpp | 57 ++++++++++++++++++++++++++++++<wbr>++++++<br>
src/amd/addrlib/gfx9/<wbr>gfx9addrlib.h | 8 +++--<br>
src/amd/common/amdgpu_id.h | 10 +++++++<br>
3 files changed, 72 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/src/amd/addrlib/gfx9/<wbr>gfx9addrlib.cpp b/src/amd/addrlib/gfx9/<wbr>gfx9addrlib.cpp<br>
index 96b05de..9b25371 100644<br>
--- a/src/amd/addrlib/gfx9/<wbr>gfx9addrlib.cpp<br>
+++ b/src/amd/addrlib/gfx9/<wbr>gfx9addrlib.cpp<br>
@@ -1186,20 +1186,34 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(<br>
if (m_settings.isVega10)<br>
{<br>
m_settings.isDce12 = 1;<br>
}<br>
<br>
m_settings.metaBaseAlignFix = 1;<br>
<br>
m_settings.depthPipeXorDisable = 1;<br>
break;<br>
<br>
+ case FAMILY_RV:<br>
+ m_settings.isArcticIsland = 1;<br>
+ m_settings.isRaven = ASICREV_IS_RAVEN(<wbr>uChipRevision);<br>
+<br>
+ if (m_settings.isRaven)<br>
+ {<br>
+ m_settings.isDcn1 = 1;<br>
+ }<br>
+<br>
+ m_settings.metaBaseAlignFix = 1;<br>
+<br>
+ m_settings.depthPipeXorDisable = 1;<br>
+ break;<br>
+<br>
default:<br>
ADDR_ASSERT(!"This should be a Fusion");<br>
break;<br>
}<br>
<br>
return family;<br>
}<br>
<br>
/**<br>
******************************<wbr>******************************<wbr>******************************<wbr>******************************<br>
@@ -2727,20 +2741,49 @@ BOOL_32 Gfx9Lib::<wbr>IsValidDisplaySwizzleMode(<br>
case ADDR_SW_64KB_R_X:<br>
case ADDR_SW_VAR_D_X:<br>
case ADDR_SW_VAR_R_X:<br>
support = (pIn->bpp <= 64);<br>
break;<br>
<br>
default:<br>
break;<br>
}<br>
}<br>
+ else if (m_settings.isDcn1)<br>
+ {<br>
+ switch (swizzleMode)<br>
+ {<br>
+ case ADDR_SW_4KB_D:<br>
+ case ADDR_SW_64KB_D:<br>
+ case ADDR_SW_VAR_D:<br>
+ case ADDR_SW_64KB_D_T:<br>
+ case ADDR_SW_4KB_D_X:<br>
+ case ADDR_SW_64KB_D_X:<br>
+ case ADDR_SW_VAR_D_X:<br>
+ support = (pIn->bpp == 64);<br>
+ break;<br>
+<br>
+ case ADDR_SW_LINEAR:<br>
+ case ADDR_SW_4KB_S:<br>
+ case ADDR_SW_64KB_S:<br>
+ case ADDR_SW_VAR_S:<br>
+ case ADDR_SW_64KB_S_T:<br>
+ case ADDR_SW_4KB_S_X:<br>
+ case ADDR_SW_64KB_S_X:<br>
+ case ADDR_SW_VAR_S_X:<br>
+ support = (pIn->bpp <= 64);<br>
+ break;<br>
+<br>
+ default:<br>
+ break;<br>
+ }<br>
+ }<br>
else<br>
{<br>
ADDR_NOT_IMPLEMENTED();<br>
}<br>
<br>
return support;<br>
}<br>
<br>
/**<br>
******************************<wbr>******************************<wbr>******************************<wbr>******************************<br>
@@ -3188,20 +3231,34 @@ ADDR_E_RETURNCODE Gfx9Lib::<wbr>HwlGetPreferredSurfaceSetting(<br>
else if (m_settings.isDce12)<br>
{<br>
if (pIn->bpp != 32)<br>
{<br>
blockSet.micro = FALSE;<br>
}<br>
<br>
// DCE12 does not support display surface to be _T swizzle mode<br>
prtXor = FALSE;<br>
}<br>
+ else if (m_settings.isDcn1)<br>
+ {<br>
+ // _R is not supported by Dcn1<br>
+ if (pIn->bpp == 64)<br>
+ {<br>
+ swType = ADDR_SW_D;<br>
+ }<br>
+ else<br>
+ {<br>
+ swType = ADDR_SW_S;<br>
+ }<br>
+<br>
+ blockSet.micro = FALSE;<br>
+ }<br>
else<br>
{<br>
ADDR_NOT_IMPLEMENTED();<br>
returnCode = ADDR_NOTSUPPORTED;<br>
}<br>
}<br>
}<br>
}<br>
<br>
if ((numFrags > 1) &&<br>
diff --git a/src/amd/addrlib/gfx9/<wbr>gfx9addrlib.h b/src/amd/addrlib/gfx9/<wbr>gfx9addrlib.h<br>
index 73d51f1..9623610 100644<br>
--- a/src/amd/addrlib/gfx9/<wbr>gfx9addrlib.h<br>
+++ b/src/amd/addrlib/gfx9/<wbr>gfx9addrlib.h<br>
@@ -47,25 +47,27 @@ namespace V2<br>
* @brief GFX9 specific settings structure.<br>
******************************<wbr>******************************<wbr>******************************<wbr>******************************<br>
*/<br>
struct Gfx9ChipSettings<br>
{<br>
struct<br>
{<br>
// Asic/Generation name<br>
UINT_32 isArcticIsland : 1;<br>
UINT_32 isVega10 : 1;<br>
- UINT_32 reserved0 : 30;<br>
+ UINT_32 isRaven : 1;<br>
+ UINT_32 reserved0 : 29;<br>
<br>
// Display engine IP version name<br>
UINT_32 isDce12 : 1;<br>
- UINT_32 reserved1 : 31;<br>
+ UINT_32 isDcn1 : 1;<br>
+ UINT_32 reserved1 : 29;<br></blockquote></div></div></div><div dir="auto"><br></div><div dir="auto">The above reserved1 should be 30 bits to make an even 32, not sure it matters but looks off.</div><div dir="auto"><br></div><div dir="auto">BR</div><div dir="auto">Nils</div><div dir="auto"><br></div><div dir="auto">[snip]</div><div dir="auto"><div class="gmail_extra" dir="auto"><br></div></div></div>