<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Fri, May 12, 2017 at 4:38 PM, Anuj Phogat <span dir="ltr"><<a href="mailto:anuj.phogat@gmail.com" target="_blank">anuj.phogat@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Ben Widawsky <<a href="mailto:benjamin.widawsky@intel.com">benjamin.widawsky@intel.com</a>><br>
<br>
GEN10 requires flushing all previous pipe controls before issuing a render<br>
target cache flush. The docs seem to fairly explicitly say this is gen10 only.<br>
<br>
V2 (by Anuj): Use flags & PIPE_CONTROL_RENDER_TARGET_<wbr>FLUSH check. (Ilia)<br>
              Use recursive call to brw_emit_pipe_control_flush().<br>
<br>
Signed-off-by: Ben Widawsky <<a href="mailto:benjamin.widawsky@intel.com">benjamin.widawsky@intel.com</a>><br>
Signed-off-by: Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com">anuj.phogat@gmail.com</a>><br>
---<br>
 src/mesa/drivers/dri/i965/brw_<wbr>pipe_control.c | 11 +++++++++++<br>
 1 file changed, 11 insertions(+)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_pipe_control.c b/src/mesa/drivers/dri/i965/<wbr>brw_pipe_control.c<br>
index f4ede2d..ecf2fac 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_pipe_control.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_pipe_control.c<br>
@@ -128,6 +128,17 @@ brw_emit_pipe_control_flush(<wbr>struct brw_context *brw, uint32_t flags)<br>
          brw_emit_pipe_control_flush(<wbr>brw, 0);<br>
       }<br>
<br>
+      if (brw->gen == 10 && (flags & PIPE_CONTROL_RENDER_TARGET_<wbr>FLUSH)) {<br>
+        /* Hardware workaround: CNL<br>
+         *<br>
+         * "Before sending a PIPE_CONTROL command with bit 12 set, SW<br>
+         * must issue another PIPE_CONTROL with Render Target Cache<br>
+         * Flush Enable (bit 12) = 0 and Pipe Control Flush Enable<br>
+         * (bit 7) = 1."<br></blockquote><div><br></div><div>A more specific spec citation would be good.  Maybe something like:<br><br></div><div>From the "Gen10 Workarounds" page:<br><br></div><div>In any case, the workaround looks correct although the docs say it only applies to A0 stepping.  Is this still even needed?<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+         */<br>
+         brw_emit_pipe_control_flush(<wbr>brw, PIPE_CONTROL_FLUSH_ENABLE);<br>
+      }<br>
+<br>
       BEGIN_BATCH(6);<br>
       OUT_BATCH(_3DSTATE_PIPE_<wbr>CONTROL | (6 - 2));<br>
       OUT_BATCH(flags);<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.9.3<br>
<br>
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</font></span></blockquote></div><br></div></div>