<div dir="ltr">Perhaps this should probably be the last patch in the series as it's the one that actually enables CNL support? Otherwise, you could get a commit with PCI ids but a completely busted driver. </div><div class="gmail_extra"> <div class="gmail_quote">On Fri, May 12, 2017 at 4:38 PM, Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com" target="_blank">anuj.phogat@gmail.com</a>> wrote: <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Ben Widawsky <<a href="mailto:benjamin.widawsky@intel.com">benjamin.widawsky@intel.com</a>> v2 (Anuj): Rebased on master and updated pci ids Remove redundant initialization of max_wm_threads to 64 * 12. For gen9+ max_wm_threads are initialized in gen_get_device_info(). Signed-off-by: Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com">anuj.phogat@gmail.com</a>> Signed-off-by: Ben Widawsky <<a href="mailto:benjamin.widawsky@intel.com">benjamin.widawsky@intel.com</a>> --- include/pci_ids/i965_pci_ids.h | 12 ++++++++ src/intel/common/gen_device_info.c | 58 ++++++++++++++++++++++++++++++++++++++ src/intel/common/gen_device_info.h | 1 + 3 files changed, 71 insertions(+) diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index 17504f5..b296359 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -165,3 +165,15 @@ CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 (Kaby Lake GT3)") CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4") CHIPSET(0x3184, glk, "Intel(R) HD Graphics (Geminilake)") CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)") +CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)") +CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)") +CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)") +CHIPSET(0x5A42, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)") +CHIPSET(0x5A44, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)") +CHIPSET(0x5A59, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)") +CHIPSET(0x5A5A, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)") +CHIPSET(0x5A5C, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)") +CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)") +CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)") +CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)") +CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)") diff --git a/src/intel/common/gen_device_info.c b/src/intel/common/gen_device_info.c index 47aed9d..87edb94 100644 --- a/src/intel/common/gen_device_info.c +++ b/src/intel/common/gen_device_info.c @@ -555,6 +555,64 @@ static const struct gen_device_info gen_device_info_glk_2x6 = { GEN9_LP_FEATURES_2X6 }; +#define GEN10_HW_INFO \ + .gen = 10, \ + .max_vs_threads = 728, \ + .max_gs_threads = 432, \ + .max_tcs_threads = 432, \ + .max_tes_threads = 624, \ + .max_cs_threads = 56, \ + .urb = { \ + .size = 256, \ + .min_entries = { \ + [MESA_SHADER_VERTEX] = 64, \ + [MESA_SHADER_TESS_EVAL] = 34, \ + }, \ + .max_entries = { \ + [MESA_SHADER_VERTEX] = 3936, \ + [MESA_SHADER_TESS_CTRL] = 896, \ + [MESA_SHADER_TESS_EVAL] = 2064, \ + [MESA_SHADER_GEOMETRY] = 832, \ + }, \ + } + +#define GEN10_FEATURES(_gt, _slices, _l3) \ + GEN8_FEATURES, \ + GEN10_HW_INFO, \ + .gt = _gt, .num_slices = _slices, .l3_banks = _l3 + +static const struct gen_device_info gen_device_info_cnl_2x8 = { + /* GT0.5 */ + GEN10_FEATURES(1, 1, 2) +}; + +static const struct gen_device_info gen_device_info_cnl_3x8 = { + /* GT1 */ + GEN10_FEATURES(1, 1, 3) +}; + +static const struct gen_device_info gen_device_info_cnl_4x8 = { + /* GT 1.5 */ + GEN10_FEATURES(1, 2, 6) +}; + +static const struct gen_device_info gen_device_info_cnl_5x8 = { + /* GT2 */ + GEN10_FEATURES(2, 2, 6) +}; + +static const struct gen_device_info gen_device_info_cnl_gt1 = { + GEN10_FEATURES(1, 1, 3) +}; + +static const struct gen_device_info gen_device_info_cnl_gt2 = { + GEN10_FEATURES(2, 2, 6) +}; + +static const struct gen_device_info gen_device_info_cnl_gt3 = { + GEN10_FEATURES(3, 4, 12) +}; + bool gen_get_device_info(int devid, struct gen_device_info *devinfo) { diff --git a/src/intel/common/gen_device_info.h b/src/intel/common/gen_device_info.h index 80676d0..6207630 100644 --- a/src/intel/common/gen_device_info.h +++ b/src/intel/common/gen_device_info.h @@ -96,6 +96,7 @@ struct gen_device_info * to change, so we program @max_cs_threads as the lower maximum. */ unsigned num_slices; + unsigned l3_banks; unsigned max_vs_threads; /**< Maximum Vertex Shader threads */ unsigned max_tcs_threads; /**< Maximum Hull Shader threads */ unsigned max_tes_threads; /**< Maximum Domain Shader threads */ -- 2.9.3 _______________________________________________ mesa-dev mailing list <a href="mailto:mesa-dev@lists.freedesktop.org">mesa-dev@lists.freedesktop.org</a> <a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev" rel="noreferrer" target="_blank">https://lists.freedesktop.org/mailman/listinfo/mesa-dev</a> </blockquote></div> </div>