<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Wed, Jun 14, 2017 at 12:00 PM, Pohjolainen, Topi <span dir="ltr"><<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="HOEnZb"><div class="h5">On Tue, Jun 06, 2017 at 10:00:06PM -0700, Jason Ekstrand wrote:<br>
> ---<br>
> src/mesa/drivers/dri/i965/brw_<wbr>blorp.c | 106 ++++++++++++++++++++++++++++++<wbr>++++<br>
> src/mesa/drivers/dri/i965/brw_<wbr>blorp.h | 4 ++<br>
> src/mesa/drivers/dri/i965/brw_<wbr>clear.c | 6 ++<br>
> 3 files changed, 116 insertions(+)<br>
><br>
> diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_blorp.c b/src/mesa/drivers/dri/i965/<wbr>brw_blorp.c<br>
> index 38925d9..a46b624 100644<br>
> --- a/src/mesa/drivers/dri/i965/<wbr>brw_blorp.c<br>
> +++ b/src/mesa/drivers/dri/i965/<wbr>brw_blorp.c<br>
> @@ -930,6 +930,112 @@ brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,<br>
> }<br>
><br>
> void<br>
> +brw_blorp_clear_depth_<wbr>stencil(struct brw_context *brw,<br>
> + struct gl_framebuffer *fb,<br>
> + GLbitfield mask, bool partial_clear)<br>
> +{<br>
> + const struct gl_context *ctx = &brw->ctx;<br>
> + struct gl_renderbuffer *depth_rb =<br>
> + fb->Attachment[BUFFER_DEPTH].<wbr>Renderbuffer;<br>
> + struct gl_renderbuffer *stencil_rb =<br>
> + fb->Attachment[BUFFER_STENCIL]<wbr>.Renderbuffer;<br>
> +<br>
> + if (!depth_rb || ctx->Depth.Mask == GL_FALSE)<br>
> + mask &= ~BUFFER_BIT_DEPTH;<br>
> +<br>
> + if (!stencil_rb || (ctx->Stencil.WriteMask[0] & 0xff) == 0)<br>
> + mask &= ~BUFFER_BIT_STENCIL;<br>
> +<br>
> + if (!(mask & (BUFFER_BITS_DEPTH_STENCIL)))<br>
> + return;<br>
> +<br>
> + uint32_t x0, x1, y0, y1, rb_name, rb_height;<br>
> + if (depth_rb) {<br>
> + rb_name = depth_rb->Name;<br>
> + rb_height = depth_rb->Height;<br>
> + if (stencil_rb) {<br>
> + assert(depth_rb->Width == stencil_rb->Width);<br>
> + assert(depth_rb->Height == stencil_rb->Height);<br>
> + }<br>
> + } else {<br>
> + assert(stencil_rb);<br>
> + rb_name = stencil_rb->Name;<br>
> + rb_height = stencil_rb->Height;<br>
> + }<br>
> +<br>
> + x0 = fb->_Xmin;<br>
> + x1 = fb->_Xmax;<br>
> + if (rb_name != 0) {<br>
> + y0 = fb->_Ymin;<br>
> + y1 = fb->_Ymax;<br>
> + } else {<br>
> + y0 = rb_height - fb->_Ymax;<br>
> + y1 = rb_height - fb->_Ymin;<br>
> + }<br>
> +<br>
> + /* If the clear region is empty, just return. */<br>
> + if (x0 == x1 || y0 == y1)<br>
> + return;<br>
> +<br>
> + unsigned level, layer, num_layers;<br>
> + struct isl_surf isl_tmp[4];<br>
> + struct blorp_surf depth_surf, stencil_surf;<br>
> +<br>
> + if (mask & BUFFER_BIT_DEPTH) {<br>
> + struct intel_renderbuffer *irb = intel_renderbuffer(depth_rb);<br>
> + struct intel_mipmap_tree *depth_mt =<br>
> + find_miptree(GL_DEPTH_BUFFER_<wbr>BIT, irb);<br>
> +<br>
> + level = irb->mt_level;<br>
> + layer = irb_logical_mt_layer(irb);<br>
> + num_layers = fb->MaxNumLayers ? irb->layer_count : 1;<br>
> +<br>
> + intel_miptree_set_all_slices_<wbr>need_depth_resolve(depth_mt, level);<br>
> +<br>
> + unsigned depth_level = level;<br>
> + blorp_surf_for_miptree(brw, &depth_surf, depth_mt, true,<br>
> + (1 << ISL_AUX_USAGE_HIZ),<br>
> + &depth_level, layer, num_layers, &isl_tmp[0]);<br>
> + assert(depth_level == level);<br>
> + }<br>
> +<br>
> + uint8_t stencil_mask = 0;<br>
> + if (mask & BUFFER_BIT_STENCIL) {<br>
> + struct intel_renderbuffer *irb = intel_renderbuffer(stencil_rb)<wbr>;<br>
> + struct intel_mipmap_tree *stencil_mt =<br>
> + find_miptree(GL_STENCIL_<wbr>BUFFER_BIT, irb);<br>
> +<br>
> + if (mask & BUFFER_BIT_DEPTH) {<br>
> + assert(level == irb->mt_level);<br>
> + assert(layer == irb_logical_mt_layer(irb));<br>
> + assert(num_layers == fb->MaxNumLayers ? irb->layer_count : 1);<br>
> + } else {<br>
> + level = irb->mt_level;<br>
> + layer = irb_logical_mt_layer(irb);<br>
> + num_layers = fb->MaxNumLayers ? irb->layer_count : 1;<br>
> + }<br>
> +<br>
> + stencil_mask = ctx->Stencil.WriteMask[0] & 0xff;<br>
> +<br>
> + unsigned stencil_level = level;<br>
> + blorp_surf_for_miptree(brw, &stencil_surf, stencil_mt, true,<br>
> + (1 << ISL_AUX_USAGE_HIZ),<br>
<br>
</div></div>Why do we set hiz for stencil?<br>
<br>
I noticed that anv_blorp.c::anv_<wbr>CmdClearDepthStencilImage() sets it to NONE<br>
for depth and stencil while get_blorp_surf_for_anv_image() has code to take<br>
the HIZ usage away for stencil (if given).<br></blockquote><div><br></div><div>No reason. I'm happy to make it 0 for no aux support on stencil. <br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Otherwise looks good to me:<br>
<br>
Reviewed-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>><br><div><div class="h5"></div></div></blockquote><div><br></div><div>Thanks!<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div class="h5">
> + &stencil_level, layer, num_layers, &isl_tmp[2]);<br>
> + }<br>
> +<br>
> + assert((mask & BUFFER_BIT_DEPTH) || stencil_mask);<br>
> +<br>
> + struct blorp_batch batch;<br>
> + blorp_batch_init(&brw->blorp, &batch, brw, 0);<br>
> + blorp_clear_depth_stencil(&<wbr>batch, &depth_surf, &stencil_surf,<br>
> + level, layer, num_layers,<br>
> + x0, y0, x1, y1,<br>
> + (mask & BUFFER_BIT_DEPTH), ctx->Depth.Clear,<br>
> + stencil_mask, ctx->Stencil.Clear);<br>
> + blorp_batch_finish(&batch);<br>
> +}<br>
> +<br>
> +void<br>
> brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt,<br>
> unsigned level, unsigned layer)<br>
> {<br>
> diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_blorp.h b/src/mesa/drivers/dri/i965/<wbr>brw_blorp.h<br>
> index 8743d96..868301f 100644<br>
> --- a/src/mesa/drivers/dri/i965/<wbr>brw_blorp.h<br>
> +++ b/src/mesa/drivers/dri/i965/<wbr>brw_blorp.h<br>
> @@ -62,6 +62,10 @@ brw_blorp_copy_miptrees(struct brw_context *brw,<br>
> bool<br>
> brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,<br>
> GLbitfield mask, bool partial_clear, bool encode_srgb);<br>
> +void<br>
> +brw_blorp_clear_depth_<wbr>stencil(struct brw_context *brw,<br>
> + struct gl_framebuffer *fb,<br>
> + GLbitfield mask, bool partial_clear);<br>
><br>
> void<br>
> brw_blorp_resolve_color(struct brw_context *brw,<br>
> diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_clear.c b/src/mesa/drivers/dri/i965/<wbr>brw_clear.c<br>
> index 664342d..57e5f16 100644<br>
> --- a/src/mesa/drivers/dri/i965/<wbr>brw_clear.c<br>
> +++ b/src/mesa/drivers/dri/i965/<wbr>brw_clear.c<br>
> @@ -293,6 +293,12 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)<br>
> }<br>
> }<br>
><br>
> + if (brw->gen >= 6 && (mask & BUFFER_BITS_DEPTH_STENCIL)) {<br>
> + brw_blorp_clear_depth_stencil(<wbr>brw, fb, mask, partial_clear);<br>
> + debug_mask("blorp depth/stencil", mask & BUFFER_BITS_DEPTH_STENCIL);<br>
> + mask &= ~BUFFER_BITS_DEPTH_STENCIL;<br>
> + }<br>
> +<br>
> GLbitfield tri_mask = mask & (BUFFER_BITS_COLOR |<br>
> BUFFER_BIT_STENCIL |<br>
> BUFFER_BIT_DEPTH);<br>
> --<br>
> 2.5.0.400.gff86faf<br>
><br>
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</blockquote></div><br></div></div>