<div dir="ltr">This patch makes the assumption that, if stencil_irb != NULL then depth_irb != NULL.  I did a bunch of digging and I am now convinced that this is a fine assumption.  Specifically, in intel_renderbuffer_format() in intel_fbo.c, we map all STENCIL_INDEX internal formats to Z24_UNORM_S8_UINT on gen4-5.<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, May 22, 2017 at 12:12 PM, Topi Pohjolainen <span dir="ltr"><<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">In case of gen < 6 stencil (if present) is always combined with<br>
depth. Both stencil and depth attachments point to the same<br>
physical surface.<br>
Alignment workaround starts by considering depth and updates<br>
stencil accordingly. Current logic continues with stencil and<br>
in vain considers the case where depth would refer to different<br>
surface than stencil.<br>
<br>
Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>><br>
---<br>
 src/mesa/drivers/dri/i965/brw_<wbr>misc_state.c | 63 ++++++------------------------<br>
</span> 1 file changed, 12 insertions(+), 51 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c b/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
index 6ea1fb0..9fe3655 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
@@ -295,28 +295,14 @@ brw_workaround_depthstencil_<wbr>alignment(struct brw_context *brw,<br>
<span class="">       }<br>
<br>
       if (stencil_irb) {<br>
-         stencil_mt = get_stencil_miptree(stencil_<wbr>irb);<br>
-         intel_miptree_get_image_<wbr>offset(stencil_mt,<br>
-                                        stencil_irb->mt_level,<br>
-                                        stencil_irb->mt_layer,<br>
-                                        &stencil_draw_x, &stencil_draw_y);<br>
-         int stencil_tile_x = stencil_draw_x & tile_mask_x;<br>
-         int stencil_tile_y = stencil_draw_y & tile_mask_y;<br>
-<br>
-         /* If stencil doesn't match depth, then we'll need to rebase stencil<br>
-          * as well.  (if we hadn't decided to rebase stencil before, the<br>
-          * post-stencil depth test will also rebase depth to try to match it<br>
-          * up).<br>
-          */<br>
-         if (tile_x != stencil_tile_x ||<br>
-             tile_y != stencil_tile_y) {<br>
-            rebase_stencil = true;<br>
-         }<br>
+         assert(stencil_irb->mt == depth_irb->mt);<br>
+         assert(stencil_irb->mt_level == depth_irb->mt_level);<br>
+         assert(stencil_irb->mt_layer == depth_irb->mt_layer);<br>
       }<br>
    }<br>
<br>
</span>    /* If we have (just) stencil, check it for ignored low bits as well */<br>
-   if (stencil_irb) {<br>
+   if (!depth_irb && stencil_irb) {<br>
       intel_miptree_get_image_<wbr>offset(stencil_mt,<br>
                                      stencil_irb->mt_level,<br>
                                      stencil_irb->mt_layer,<br>
<span class="">@@ -334,6 +320,14 @@ brw_workaround_depthstencil_<wbr>alignment(struct brw_context *brw,<br>
    }<br>
<br>
    if (rebase_stencil) {<br>
+      /* If stencil needs rebase, there isn't a depth attachment and the<br>
+       * combined depth-stencil is used for stencil only. Otherwise in case<br>
+       * depth attachment is present both stencil and depth point to the same<br>
+       * miptree. Rebase of depth is considered first updating stencil<br>
+       * attachment accordingly - hence stencil is rebased only if there is no<br>
+       * depth attachment.<br>
+       */<br>
+      assert(!depth_irb);<br>
       perf_debug("HW workaround: blitting stencil level %d to a temporary "<br>
                  "to fix alignment (stencil tile offset %d,%d)\n",<br>
                  stencil_irb->mt_level, stencil_tile_x, stencil_tile_y);<br>
</span>@@ -347,39 +341,6 @@ brw_workaround_depthstencil_<wbr>alignment(struct brw_context *brw,<br>
                                      &stencil_draw_x, &stencil_draw_y);<br>
<div><div class="h5">       stencil_tile_x = stencil_draw_x & tile_mask_x;<br>
       stencil_tile_y = stencil_draw_y & tile_mask_y;<br>
-<br>
-      if (depth_irb && depth_irb->mt == stencil_irb->mt) {<br>
-         intel_miptree_reference(&<wbr>depth_irb->mt, stencil_irb->mt);<br>
-         intel_renderbuffer_set_draw_<wbr>offset(depth_irb);<br>
-      } else if (depth_irb && !rebase_depth) {<br>
-         if (tile_x != stencil_tile_x ||<br>
-             tile_y != stencil_tile_y) {<br>
-            perf_debug("HW workaround: blitting depth level %d to a temporary "<br>
-                       "to match stencil level %d alignment (depth tile offset "<br>
-                       "%d,%d, stencil offset %d,%d)\n",<br>
-                       depth_irb->mt_level,<br>
-                       stencil_irb->mt_level,<br>
-                       tile_x, tile_y,<br>
-                       stencil_tile_x, stencil_tile_y);<br>
-<br>
-            intel_renderbuffer_move_to_<wbr>temp(brw, depth_irb, invalidate_depth);<br>
-<br>
-            tile_x = depth_irb->draw_x & tile_mask_x;<br>
-            tile_y = depth_irb->draw_y & tile_mask_y;<br>
-<br>
-            if (stencil_irb && stencil_irb->mt == depth_mt) {<br>
-               intel_miptree_reference(&<wbr>stencil_irb->mt, depth_irb->mt);<br>
-               intel_renderbuffer_set_draw_<wbr>offset(stencil_irb);<br>
-            }<br>
-<br>
-            WARN_ONCE(stencil_tile_x != tile_x ||<br>
-                      stencil_tile_y != tile_y,<br>
-                      "Rebased stencil tile offset (%d,%d) doesn't match depth "<br>
-                      "tile offset (%d,%d).\n",<br>
-                      stencil_tile_x, stencil_tile_y,<br>
-                      tile_x, tile_y);<br>
-         }<br>
-      }<br>
    }<br>
<br>
</div></div>    if (!depth_irb) {<br>
<div class="HOEnZb"><div class="h5">--<br>
2.9.3<br>
<br>
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</div></div></blockquote></div><br></div>