<div dir="ltr">Do intel run mesa through any of their test boxes like they do with kernel patches?</div><br><div class="gmail_quote"><div dir="ltr">On Wed, 21 Jun 2017 at 19:23 Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Wed, Jun 21, 2017 at 11:20 AM, Pohjolainen, Topi <span dir="ltr"><<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span>On Wed, Jun 21, 2017 at 11:16:39AM -0700, Jason Ekstrand wrote:<br>
> Bugzilla: <a href="https://bugs.freedesktop.org/show_bug.cgi?id=101538" rel="noreferrer" target="_blank">https://bugs.freedesktop.org/show_bug.cgi?id=101538</a><br>
> Bugzilla: <a href="https://bugs.freedesktop.org/show_bug.cgi?id=101539" rel="noreferrer" target="_blank">https://bugs.freedesktop.org/show_bug.cgi?id=101539</a><br>
<br>
</span>I guess also:<br>
<br>
<a href="https://bugs.freedesktop.org/show_bug.cgi?id=101535" rel="noreferrer" target="_blank">https://bugs.freedesktop.org/show_bug.cgi?id=101535</a><br>
<br>
Thanks for the quick fix!!<br></blockquote><div><br></div></div></div></div><div dir="ltr"><div class="gmail_extra"><div class="gmail_quote"><div>No problem. I've landed it now so peoples desktops can start working again.<br></div></div></div></div><div dir="ltr"><div class="gmail_extra"><div class="gmail_quote"><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Reviewed-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com" target="_blank">topi.pohjolainen@intel.com</a>><br>
<div><div class="m_6023022784355772762h5"><br>
> Cc: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com" target="_blank">topi.pohjolainen@intel.com</a>><br>
> ---<br>
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 ++++++----<br>
> 1 file changed, 6 insertions(+), 4 deletions(-)<br>
><br>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c<br>
> index abc7f98..3b7262f 100644<br>
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c<br>
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c<br>
> @@ -1672,8 +1672,9 @@ intel_miptree_alloc_mcs(struct brw_context *brw,<br>
> * calculate equivalent MCS surface against it.<br>
> */<br>
> intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);<br>
> - assert(isl_surf_get_mcs_surf(&brw->isl_dev, &temp_main_surf,<br>
> - &temp_mcs_surf));<br>
> + MAYBE_UNUSED bool ok =<br>
> + isl_surf_get_mcs_surf(&brw->isl_dev, &temp_main_surf, &temp_mcs_surf);<br>
> + assert(ok);<br>
><br>
> /* Buffer needs to be initialised requiring the buffer to be immediately<br>
> * mapped to cpu space for writing. Therefore do not use the gpu access<br>
> @@ -1832,8 +1833,9 @@ intel_miptree_alloc_hiz(struct brw_context *brw,<br>
> struct isl_surf temp_hiz_surf;<br>
><br>
> intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);<br>
> - assert(isl_surf_get_hiz_surf(&brw->isl_dev, &temp_main_surf,<br>
> - &temp_hiz_surf));<br>
> + MAYBE_UNUSED bool ok =<br>
> + isl_surf_get_hiz_surf(&brw->isl_dev, &temp_main_surf, &temp_hiz_surf);<br>
> + assert(ok);<br>
><br>
> const uint32_t alloc_flags = BO_ALLOC_FOR_RENDER;<br>
> mt->hiz_buf = intel_alloc_aux_buffer(brw, "hiz-miptree",<br>
> --<br>
> 2.5.0.400.gff86faf<br>
><br>
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</blockquote></div></div></div>
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