<div dir="ltr"><div>9-16 are<br><br></div>Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jul 17, 2017 at 6:35 AM, Topi Pohjolainen <span dir="ltr"><<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Current logic calls intel_renderbuffer_set_draw_<wbr>offset() which in<br>
turn tries to calculate x and y offset against layer/level settings<br>
that are against the original miptree actually having sufficient<br>
levels/layers. This returns correctly x=0 y=0 regardless of the given<br>
layer/level only because one calls intel_miptree_get_image_<wbr>offset()<br>
which goes and consults miptree offset table which in turn luckily<br>
contains entries for max-mipmap levels, all initialised to zero even<br>
in case of non-mipmapped.<br>
<br>
This patch stops consulting the table and simply sets the draw<br>
offsets to zero that are compatible with the single slice miptree<br>
backing the renderbuffer.<br>
This prepares for ISL based miptrees that calculate offsets<br>
on-demand and do not tolerate levels beyond what the miptree has.<br>
<br>
Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>><br>
---<br>
src/mesa/drivers/dri/i965/brw_<wbr>misc_state.c | 10 ++++++----<br>
1 file changed, 6 insertions(+), 4 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c b/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
index d242aa4991..e9b3b06421 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
@@ -168,9 +168,11 @@ rebase_depth_stencil(struct brw_context *brw, struct intel_renderbuffer *irb,<br>
irb->mt_level, tile_x, tile_y);<br>
intel_renderbuffer_move_to_<wbr>temp(brw, irb, invalidate);<br>
<br>
- /* Get the new offset. */<br>
- tile_x = irb->draw_x & tile_mask_x;<br>
- tile_y = irb->draw_y & tile_mask_y;<br>
+ /* There is now only single slice miptree. */<br>
+ brw->depthstencil.tile_x = 0;<br>
+ brw->depthstencil.tile_y = 0;<br>
+ brw->depthstencil.depth_offset = 0;<br>
+ return true;<br>
}<br>
<br>
/* While we just tried to get everything aligned, we may have failed to do<br>
@@ -192,7 +194,7 @@ rebase_depth_stencil(struct brw_context *brw, struct intel_renderbuffer *irb,<br>
irb->draw_x & ~tile_mask_x,<br>
irb->draw_y & ~tile_mask_y);<br>
<br>
- return rebase;<br>
+ return false;<br>
}<br>
<br>
void<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.11.0<br>
<br>
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