<div dir="ltr">Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <span dir="ltr"><<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Depth buffers are always Y-tiled. In brw_miptree_choose_tiling()<br>
driver opts to use linear buffers for small and 1D but this does<br>
not apply for depth - GL_DEPTH_COMPONENT and GL_DEPTH_STENCIL_EXT<br>
are considered first.<br>
<br>
Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>><br>
---<br>
 src/mesa/drivers/dri/i965/brw_<wbr>misc_state.c   | 3 +--<br>
 src/mesa/drivers/dri/i965/<wbr>gen6_depth_state.c | 3 +--<br>
 2 files changed, 2 insertions(+), 4 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c b/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
index 0c43d2b4b2..1e3be784c5 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
@@ -383,8 +383,7 @@ brw_emit_depth_stencil_hiz(<wbr>struct brw_context *brw,<br>
    OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |<br>
              (depthbuffer_format << 18) |<br>
              (BRW_TILEWALK_YMAJOR << 26) |<br>
-             ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1)<br>
-              << 27) |<br>
+             (1 << 27) |<br>
              (depth_surface_type << 29));<br>
<br>
    if (depth_mt) {<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>gen6_depth_state.c b/src/mesa/drivers/dri/i965/<wbr>gen6_depth_state.c<br>
index 8f05b4cc1a..3e3d2c629b 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>gen6_depth_state.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>gen6_depth_state.c<br>
@@ -121,8 +121,7 @@ gen6_emit_depth_stencil_hiz(<wbr>struct brw_context *brw,<br>
              ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable */<br>
              ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */<br>
              (BRW_TILEWALK_YMAJOR << 26) |<br>
-             ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1)<br>
-              << 27) |<br>
+             (1 << 27) |<br>
              (surftype << 29));<br>
<br>
    /* 3DSTATE_DEPTH_BUFFER dw2 */<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.11.0<br>
<br>
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</font></span></blockquote></div><br></div>