<div dir="ltr">Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jul 19, 2017 at 9:45 PM, Topi Pohjolainen <span dir="ltr"><<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">v2 (Jason): Check for !ISL_SURF_DIM_3D instead of CUBE_BIT.<br>
<span class=""><br>
Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>><br>
---<br>
</span> src/intel/isl/isl.c | 41 ++++++++++++++++++++++++++++++<wbr>+++++------<br>
1 file changed, 35 insertions(+), 6 deletions(-)<br>
<br>
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c<br>
index 12ffe3bb51..7d1356f0ac 100644<br>
<div><div class="h5">--- a/src/intel/isl/isl.c<br>
+++ b/src/intel/isl/isl.c<br>
@@ -548,7 +548,8 @@ isl_choose_image_alignment_el(<wbr>const struct isl_device *dev,<br>
static enum isl_dim_layout<br>
isl_surf_choose_dim_layout(<wbr>const struct isl_device *dev,<br>
enum isl_surf_dim logical_dim,<br>
- enum isl_tiling tiling)<br>
+ enum isl_tiling tiling,<br>
+ isl_surf_usage_flags_t usage)<br>
{<br>
/* Sandy bridge needs a special layout for HiZ and stencil. */<br>
if (ISL_DEV_GEN(dev) == 6 &&<br>
@@ -584,6 +585,16 @@ isl_surf_choose_dim_layout(<wbr>const struct isl_device *dev,<br>
switch (logical_dim) {<br>
case ISL_SURF_DIM_1D:<br>
case ISL_SURF_DIM_2D:<br>
+ /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":<br>
+ *<br>
+ * The cube face textures are stored in the same way as 3D surfaces<br>
+ * are stored (see section 6.17.5 for details). For cube surfaces,<br>
+ * however, the depth is equal to the number of faces (always 6) and<br>
+ * is not reduced for each MIP.<br>
+ */<br>
+ if (ISL_DEV_GEN(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT))<br>
+ return ISL_DIM_LAYOUT_GEN4_3D;<br>
+<br>
return ISL_DIM_LAYOUT_GEN4_2D;<br>
case ISL_SURF_DIM_3D:<br>
return ISL_DIM_LAYOUT_GEN4_3D;<br>
@@ -635,8 +646,11 @@ isl_calc_phys_level0_extent_<wbr>sa(const struct isl_device *dev,<br>
break;<br>
<br>
case ISL_SURF_DIM_2D:<br>
- assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D ||<br>
- dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_<wbr>HIZ);<br>
+ if (ISL_DEV_GEN(dev) == 4 && (info->usage & ISL_SURF_USAGE_CUBE_BIT))<br>
+ assert(dim_layout == ISL_DIM_LAYOUT_GEN4_3D);<br>
+ else<br>
+ assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D ||<br>
+ dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_<wbr>HIZ);<br>
<br>
if (tiling == ISL_TILING_Ys && info->samples > 1)<br>
isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__);<br>
</div></div>@@ -952,7 +966,21 @@ isl_calc_phys_total_extent_el_<wbr>gen4_3d(<br>
<span class=""> const struct isl_format_layout *fmtl = isl_format_get_layout(info-><wbr>format);<br>
<br>
assert(info->samples == 1);<br>
- assert(phys_level0_sa->array_<wbr>len == 1);<br>
+<br>
</span>+ if (info->dim != ISL_SURF_DIM_3D) {<br>
<span class="">+ /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":<br>
+ *<br>
+ * The cube face textures are stored in the same way as 3D surfaces<br>
+ * are stored (see section 6.17.5 for details). For cube surfaces,<br>
+ * however, the depth is equal to the number of faces (always 6) and<br>
+ * is not reduced for each MIP.<br>
+ */<br>
</span>+ assert(ISL_DEV_GEN(dev) == 4);<br>
+ assert(info->usage & ISL_SURF_USAGE_CUBE_BIT);<br>
<span class="">+ assert(phys_level0_sa->array_<wbr>len == 6);<br>
+ } else {<br>
+ assert(phys_level0_sa->array_<wbr>len == 1);<br>
</span>+ }<br>
<span class=""><br>
uint32_t total_w = 0;<br>
uint32_t total_h = 0;<br>
</span>@@ -960,11 +988,12 @@ isl_calc_phys_total_extent_el_<wbr>gen4_3d(<br>
uint32_t W0 = phys_level0_sa->w;<br>
uint32_t H0 = phys_level0_sa->h;<br>
uint32_t D0 = phys_level0_sa->d;<br>
+ uint32_t A0 = phys_level0_sa->a;<br>
<br>
for (uint32_t l = 0; l < info->levels; ++l) {<br>
uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w);<br>
<span class=""> uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa->h);<br>
</span>- uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa->d);<br>
+ uint32_t level_d = info->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : A0;<br>
<span class=""><br>
uint32_t max_layers_horiz = MIN(level_d, 1u << l);<br>
uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);<br>
</span>@@ -1427,7 +1456,7 @@ isl_surf_init_s(const struct isl_device *dev,<br>
<div class="HOEnZb"><div class="h5"> isl_tiling_get_info(tiling, fmtl->bpb, &tile_info);<br>
<br>
const enum isl_dim_layout dim_layout =<br>
- isl_surf_choose_dim_layout(<wbr>dev, info->dim, tiling);<br>
+ isl_surf_choose_dim_layout(<wbr>dev, info->dim, tiling, info->usage);<br>
<br>
enum isl_msaa_layout msaa_layout;<br>
if (!isl_choose_msaa_layout(dev, info, tiling, &msaa_layout))<br>
--<br>
2.11.0<br>
<br>
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</div></div></blockquote></div><br></div>