<div dir="ltr"><div>11-15 are<br><br></div>Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jul 21, 2017 at 8:01 AM, Topi Pohjolainen <span dir="ltr"><<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>><br>
---<br>
 src/mesa/drivers/dri/i965/brw_<wbr>wm_surface_state.c | 10 +-<br>
 src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c  | 119 ++++++-----------------<br>
 2 files changed, 36 insertions(+), 93 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
index e9a50b89eb..d9daa8ec18 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
@@ -183,7 +183,7 @@ brw_emit_surface_state(struct brw_context *brw,<br>
                 brw->isl_dev.ss.align,<br>
                 surf_offset);<br>
<br>
-Â Â isl_surf_fill_state(&brw->isl_<wbr>dev, state, .surf = &surf, .view = &view,<br>
+Â Â isl_surf_fill_state(&brw->isl_<wbr>dev, state, .surf = &mt->surf, .view = &view,<br>
            .address = mt->bo->offset64 + offset,<br>
            .aux_surf = aux_surf, .aux_usage = aux_usage,<br>
            .aux_address = aux_offset,<br>
@@ -1069,7 +1069,8 @@ gen4_update_renderbuffer_<wbr>surface(struct brw_context *brw,<br>
  assert(tile_y % 2 == 0);<br>
  surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |<br>
       (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |<br>
-Â Â Â Â Â Â Â (mt->valign == 4 ? BRW_SURFACE_VERTICAL_ALIGN_<wbr>ENABLE : 0));<br>
+Â Â Â Â Â Â Â (mt->surf.image_alignment_el.<wbr>height == 4 ?<br>
+Â Â Â Â Â Â Â Â Â BRW_SURFACE_VERTICAL_ALIGN_<wbr>ENABLE : 0));<br>
<br>
  if (brw->gen < 6) {<br>
    /* _NEW_COLOR */<br>
@@ -1733,10 +1734,7 @@ update_image_surface(struct brw_context *brw,<br>
                       I915_GEM_DOMAIN_SAMPLER);<br>
     }<br>
<br>
-Â Â Â Â Â struct isl_surf surf;<br>
-Â Â Â Â Â intel_miptree_get_isl_surf(<wbr>brw, mt, &surf);<br>
-<br>
-Â Â Â Â Â isl_surf_fill_image_param(&<wbr>brw->isl_dev, param, &surf, &view);<br>
+Â Â Â Â Â isl_surf_fill_image_param(&<wbr>brw->isl_dev, param, &mt->surf, &view);<br>
     param->surface_idx = surface_idx;<br>
    }<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c<br>
index 3a2395b030..7b2f98cc1b 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c<br>
@@ -184,7 +184,8 @@ intel_miptree_supports_ccs(<wbr>struct brw_context *brw,<br>
    return false;<br>
<br>
  const bool mip_mapped = mt->first_level != 0 || mt->last_level != 0;<br>
-Â Â const bool arrayed = mt->physical_depth0 != 1;<br>
+Â Â const bool arrayed = mt->surf.logical_level0_px.<wbr>array_len > 1 ||<br>
+Â Â Â Â Â Â Â Â Â Â Â Â mt->surf.logical_level0_px.<wbr>depth > 1;<br>
<br>
  if (arrayed) {<br>
    /* Multisample surfaces with the CMS layout are not layered surfaces,<br>
@@ -940,7 +941,6 @@ miptree_create(struct brw_context *brw,<br>
    return mt;<br>
  }<br>
<br>
-Â Â struct intel_mipmap_tree *mt;<br>
  mesa_format tex_format = format;<br>
  mesa_format etc_format = MESA_FORMAT_NONE;<br>
  uint32_t alloc_flags = 0;<br>
@@ -950,52 +950,28 @@ miptree_create(struct brw_context *brw,<br>
  etc_format = (format != tex_format) ? tex_format : MESA_FORMAT_NONE;<br>
<br>
  assert((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0);<br>
-Â Â mt = intel_miptree_create_layout(<wbr>brw, target, format,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â first_level, last_level, width0,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â height0, depth0, num_samples,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â layout_flags);<br>
-Â Â if (!mt)<br>
-Â Â Â return NULL;<br>
-<br>
  if (layout_flags & MIPTREE_LAYOUT_ACCELERATED_<wbr>UPLOAD)<br>
    alloc_flags |= BO_ALLOC_FOR_RENDER;<br>
<br>
-Â Â mt->etc_format = etc_format;<br>
+Â Â const isl_tiling_flags_t tiling_flags = force_linear_tiling(layout_<wbr>flags) ?<br>
+Â Â Â ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK;<br>
+Â Â struct intel_mipmap_tree *mt = make_surface(<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â brw, target, format,<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â first_level, last_level,<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â width0, height0, depth0,<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â num_samples, tiling_flags,<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ISL_SURF_USAGE_RENDER_TARGET_<wbr>BIT |<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ISL_SURF_USAGE_TEXTURE_BIT,<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â alloc_flags, 0, NULL);<br>
+Â Â if (!mt)<br>
+Â Â Â return NULL;<br>
<br>
-Â Â if (format == MESA_FORMAT_S_UINT8) {<br>
-Â Â Â /* Align to size of W tile, 64x64. */<br>
-Â Â Â mt->bo = brw_bo_alloc_tiled_2d(brw-><wbr>bufmgr, "miptree",<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ALIGN(mt->total_width, 64),<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ALIGN(mt->total_height, 64),<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â mt->cpp,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â isl_tiling_to_i915_tiling(<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â mt->surf.tiling),<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &mt->surf.row_pitch,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â alloc_flags);<br>
-<br>
-   /* The stencil buffer has quirky pitch requirements. From the<br>
-Â Â Â Â * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER<br>
-Â Â Â Â * dword 1 bits 16:0 - Surface Pitch):<br>
-Â Â Â Â *<br>
-Â Â Â Â *Â Â The pitch must be set to 2x the value computed based on width, as<br>
-Â Â Â Â *Â Â the stencil buffer is stored with two rows interleaved.<br>
-Â Â Â Â *<br>
-Â Â Â Â * While the Ivybridge PRM lacks this comment, the BSpec contains the<br>
-Â Â Â Â * same text, and experiments indicate that this is necessary.<br>
-Â Â Â Â */<br>
-Â Â Â mt->surf.row_pitch *= 2;<br>
-Â Â } else {<br>
-Â Â Â mt->bo = brw_bo_alloc_tiled_2d(brw-><wbr>bufmgr, "miptree",<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â mt->total_width, mt->total_height,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â mt->cpp,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â isl_tiling_to_i915_tiling(<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â mt->surf.tiling),<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &mt->surf.row_pitch,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â alloc_flags);<br>
-Â Â }<br>
+Â Â mt->etc_format = etc_format;<br>
<br>
-Â Â if (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT)<br>
+Â Â if (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT) {<br>
    mt->bo->cache_coherent = false;<br>
+Â Â Â mt->is_scanout = true;<br>
+Â Â }<br>
<br>
  if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))<br>
    intel_miptree_choose_aux_<wbr>usage(brw, mt);<br>
@@ -1025,29 +1001,8 @@ intel_miptree_create(struct brw_context *brw,<br>
  if (!mt)<br>
    return NULL;<br>
<br>
-Â Â if (need_to_retile_as_x(brw, mt->bo->size, mt->surf.tiling)) {<br>
-Â Â Â const uint32_t alloc_flags =<br>
-Â Â Â Â Â (layout_flags & MIPTREE_LAYOUT_ACCELERATED_<wbr>UPLOAD) ?<br>
-Â Â Â Â Â BO_ALLOC_FOR_RENDER : 0;<br>
-Â Â Â perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",<br>
-Â Â Â Â Â Â Â Â Â mt->total_width, mt->total_height);<br>
-<br>
-Â Â Â mt->surf.tiling = ISL_TILING_X;<br>
-Â Â Â brw_bo_unreference(mt->bo);<br>
-Â Â Â mt->bo = brw_bo_alloc_tiled_2d(brw-><wbr>bufmgr, "miptree",<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â mt->total_width, mt->total_height, mt->cpp,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â isl_tiling_to_i915_tiling(<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â mt->surf.tiling),<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &mt->surf.row_pitch, alloc_flags);<br>
-Â Â }<br>
-<br>
  mt->offset = 0;<br>
<br>
-Â Â if (!mt->bo) {<br>
-Â Â Â Â intel_miptree_release(&mt);<br>
-Â Â Â Â return NULL;<br>
-Â Â }<br>
-<br>
  if (!intel_miptree_alloc_aux(brw, mt)) {<br>
    intel_miptree_release(&mt);<br>
    return NULL;<br>
@@ -1123,20 +1078,18 @@ intel_miptree_create_for_bo(<wbr>struct brw_context *brw,<br>
  assert((layout_flags & MIPTREE_LAYOUT_TILING_ANY) == 0);<br>
  assert((layout_flags & MIPTREE_LAYOUT_TILING_NONE) == 0);<br>
<br>
-Â Â layout_flags |= MIPTREE_LAYOUT_FOR_BO;<br>
-Â Â mt = intel_miptree_create_layout(<wbr>brw, target, format,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â 0, 0,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â width, height, depth,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â 1 /* num_samples */,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â layout_flags);<br>
+Â Â mt = make_surface(brw, target, format,<br>
+Â Â Â Â Â Â Â Â Â Â Â 0, 0, width, height, depth, 1,<br>
+Â Â Â Â Â Â Â Â Â Â Â 1lu << isl_tiling_from_i915_tiling(<wbr>tiling),<br>
+Â Â Â Â Â Â Â Â Â Â Â ISL_SURF_USAGE_RENDER_TARGET_<wbr>BIT |<br>
+Â Â Â Â Â Â Â Â Â Â Â ISL_SURF_USAGE_TEXTURE_BIT,<br>
+Â Â Â Â Â Â Â Â Â Â Â 0, pitch, bo);<br>
  if (!mt)<br>
    return NULL;<br>
<br>
  brw_bo_reference(bo);<br>
  mt->bo = bo;<br>
-Â Â mt->surf.row_pitch = pitch;<br>
  mt->offset = offset;<br>
-Â Â mt->surf.tiling = isl_tiling_from_i915_tiling(<wbr>tiling);<br>
<br>
  if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))<br>
    intel_miptree_choose_aux_<wbr>usage(brw, mt);<br>
@@ -1320,8 +1273,8 @@ intel_update_winsys_<wbr>renderbuffer_miptree(struct brw_context *intel,<br>
    irb->singlesample_mt = singlesample_mt;<br>
<br>
    if (!irb->mt ||<br>
-Â Â Â Â Â irb->mt->logical_width0 != width ||<br>
-Â Â Â Â Â irb->mt->logical_height0 != height) {<br>
+Â Â Â Â Â irb->mt->surf.logical_level0_<wbr>px.width != width ||<br>
+Â Â Â Â Â irb->mt->surf.logical_level0_<wbr>px.height != height) {<br>
     multisample_mt = intel_miptree_create_for_<wbr>renderbuffer(intel,<br>
                                 format,<br>
                                 width,<br>
@@ -1981,15 +1934,10 @@ intel_miptree_alloc_mcs(struct brw_context *brw,<br>
  if (!aux_state)<br>
    return false;<br>
<br>
-Â Â struct isl_surf temp_main_surf;<br>
  struct isl_surf temp_mcs_surf;<br>
<br>
-Â Â /* Create first an ISL presentation for the main color surface and let ISL<br>
-Â Â * calculate equivalent MCS surface against it.<br>
-Â Â */<br>
-Â Â intel_miptree_get_isl_surf(<wbr>brw, mt, &temp_main_surf);<br>
  MAYBE_UNUSED bool ok =<br>
-Â Â Â isl_surf_get_mcs_surf(&brw-><wbr>isl_dev, &temp_main_surf, &temp_mcs_surf);<br>
+Â Â Â isl_surf_get_mcs_surf(&brw-><wbr>isl_dev, &mt->surf, &temp_mcs_surf);<br>
  assert(ok);<br>
<br>
  /* Buffer needs to be initialised requiring the buffer to be immediately<br>
@@ -2020,15 +1968,9 @@ intel_miptree_alloc_ccs(struct brw_context *brw,<br>
  assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E ||<br>
      mt->aux_usage == ISL_AUX_USAGE_CCS_D);<br>
<br>
-Â Â struct isl_surf temp_main_surf;<br>
  struct isl_surf temp_ccs_surf;<br>
<br>
-Â Â /* Create first an ISL presentation for the main color surface and let ISL<br>
-Â Â * calculate equivalent CCS surface against it.<br>
-Â Â */<br>
-Â Â intel_miptree_get_isl_surf(<wbr>brw, mt, &temp_main_surf);<br>
-Â Â if (!isl_surf_get_ccs_surf(&brw-><wbr>isl_dev, &temp_main_surf,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &temp_ccs_surf, 0))<br>
+Â Â if (!isl_surf_get_ccs_surf(&brw-><wbr>isl_dev, &mt->surf, &temp_ccs_surf, 0))<br>
    return false;<br>
<br>
  assert(temp_ccs_surf.size &&<br>
@@ -2288,7 +2230,10 @@ intel_miptree_check_color_<wbr>resolve(const struct brw_context *brw,<br>
    return;<br>
<br>
  /* Fast color clear is supported for non-msaa arrays only on Gen8+. */<br>
-Â Â assert(brw->gen >= 8 || (layer == 0 && mt->logical_depth0 == 1));<br>
+Â Â assert(brw->gen >= 8 ||<br>
+Â Â Â Â Â (layer == 0 &&<br>
+Â Â Â Â Â Â mt->surf.logical_level0_px.<wbr>depth == 1 &&<br>
+Â Â Â Â Â Â mt->surf.logical_level0_px.<wbr>array_len == 1));<br>
<br>
  (void)level;<br>
  (void)layer;<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.11.0<br>
<br>
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</font></span></blockquote></div><br></div>