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<div class="moz-cite-prefix">Am 17.08.2017 um 06:30 schrieb Jan
Vesely:<br>
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<pre wrap="">On Wed, 2017-08-16 at 23:49 -0400, Alex Deucher wrote:
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<pre wrap="">On Wed, Aug 16, 2017 at 11:34 PM, Michel Dänzer <a class="moz-txt-link-rfc2396E" href="mailto:michel@daenzer.net"><michel@daenzer.net></a> wrote:
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<pre wrap="">On 17/08/17 12:33 PM, Aaron Watry wrote:
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<pre wrap="">On Wed, Aug 16, 2017 at 9:48 PM, Alex Deucher <a class="moz-txt-link-rfc2396E" href="mailto:alexdeucher@gmail.com"><alexdeucher@gmail.com></a> wrote:
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<pre wrap="">On Wed, Aug 16, 2017 at 10:39 PM, Michel Dänzer <a class="moz-txt-link-rfc2396E" href="mailto:michel@daenzer.net"><michel@daenzer.net></a> wrote:
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<pre wrap="">On 17/08/17 10:52 AM, Aaron Watry wrote:
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<pre wrap="">PIPE_CAP_RESOURCE_FROM_USER_MEMORY says that size must be page aligned,
but doesn't necessarily say anything about the size of those pages.
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Is there any case known so far where it's not the CPU page size?
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<pre wrap="">
It's always the CPU page size. The limitation is not a hw limitation,
it's a sw limitation with the way the kernel handles creating BOs from
user memory.
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So this won't change with the 2MB pages that are coming up for Vega?
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I don't think it will, that's only about VRAM.
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<pre wrap="">
It applies to system memory as well, e.g., transparent huge pages, or
larger page sizes in general. I don't think that affects this
however.
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<pre wrap="">
what's so special about Vega 2MB pages? I thought GPUVM fragments could
specify any size (power of 2 > 4KB) even if TLBs supports anly select
few.
I remember using 4KB, 2MB, and 1GB pages with nice performance benefits
on Kaveri (using ATS, ROCm setup).</pre>
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<br>
In general ATS works completely different to GPUVM and is rather
bound to the CPU page tables.<br>
<br>
But GPUVM on everything before Vega10 has a so called fragmentation
size in their page table entries which tell the TLB that a certain
bunch of them are consecutive and so only one of them needs to be
fetched and cached.<br>
<br>
After Vega10 we more or less have the same as on x86_64 CPUs where
you set a bit in the page directory entry to stop the fetcher and
use that address instead. This way you not only make the TLB much
faster, but also save the last layer in the page table tree.<br>
<br>
Christian.<br>
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<blockquote type="cite"
cite="mid:1502944203.10286.5.camel@rutgers.edu">
<pre wrap="">
Jan
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<pre wrap="">
Alex
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<pre wrap="">If so, I guess I can just use getpagesize() in patch 2 for now and skip the CAP.
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<pre wrap="">
Right.
--
Earthling Michel Dänzer | <a class="moz-txt-link-freetext" href="http://www.amd.com">http://www.amd.com</a>
Libre software enthusiast | Mesa and X developer
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