<div dir="ltr">Given the fact that we're whacking BRW_NEW_AUX_USAGE whenever aux_state changes, I don't think we need this. First off, for most surfaces, the aux buffer is created when the surface is created at which point it's never been referenced with a SURFACE_STATE and we don't need to flag new state. The only case where it's not allocated immediately is for single-sampled fast-clears (CCS_D); in that case we do a fast clear and then does an intel_miptree_set_aux_state so it will get flagged at that point.<br><div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Sep 15, 2017 at 3:02 AM, Iago Toral Quiroga <span dir="ltr"><<a href="mailto:itoral@igalia.com" target="_blank">itoral@igalia.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Fixes a regression introduced with b96313c0e1289b296d7, which removed<br>
BRW_NEW_BLORP for a bunch of SURFACE_STATE setup code, including render<br>
targets, on the basis that blorp invalidates binding tables but not<br>
surface states, however, at least on Broadwell, this caused a regression<br>
in a CTS test, which Ken and Jason tracked down to the fact that we<br>
are not uploading new render target surface states after allocating<br>
new CCS_D surfaces for fast clears (which allocation is deferred until<br>
an actual clear occurs).<br>
<br>
The reason this only fails in BDW is that on SKL+ we use CCS_E which<br>
is allocated up front so it exists in the initial surface state, the<br>
problem can be reproduced in these platforms too if we use<br>
INTEL_DEBUG=norcb to force the CCS_D path.<br>
<br>
This patch ensures that any time we create a new aux surface we<br>
flag BRW_NEW_AUX_STATE so we upload new surface state for it. In theory,<br>
we only need to do this necessarily for CCS_D because it is the only<br>
kind for which allocation can be deferred, all the others are allocated<br>
in the initial state so they will always be uploaded, but it is probably<br>
not a bad idea to flag all of them anyway.<br>
<br>
Credit goes to Jason and Ken for figuring out the reason for the<br>
regression.<br>
<br>
Fixes:<br>
KHR-GL45.transform_feedback.<wbr>draw_xfb_test<br>
---<br>
src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c | 5 +++++<br>
1 file changed, 5 insertions(+)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c<br>
index 32394ca3aa..8a809a7320 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c<br>
@@ -953,6 +953,8 @@ create_ccs_buf_for_image(<wbr>struct brw_context *brw,<br>
mt->mcs_buf->qpitch = 0;<br>
mt->mcs_buf->surf = temp_ccs_surf;<br>
<br>
+ brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;<br>
+<br>
return true;<br>
}<br>
<br>
@@ -1731,6 +1733,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,<br>
}<br>
<br>
mt->aux_state = aux_state;<br>
+ brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;<br>
<br>
intel_miptree_init_mcs(brw, mt, 0xFF);<br>
<br>
@@ -1780,6 +1783,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,<br>
}<br>
<br>
mt->aux_state = aux_state;<br>
+ brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;<br>
<br>
return true;<br>
}<br>
@@ -1851,6 +1855,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,<br>
intel_miptree_level_enable_<wbr>hiz(brw, mt, level);<br>
<br>
mt->aux_state = aux_state;<br>
+ brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;<br>
<br>
return true;<br>
}<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.11.0<br>
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