<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Sat, Oct 28, 2017 at 11:36 AM, Jason Ekstrand <<a href="mailto:jason@jlekstrand.net" target="_blank">jason@jlekstrand.net</a>> wrote: <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">This series adds support for cross-stage optimizations in anv. There are a few patches from Jordan's shader cache series in here that I wanted because they made my life easier. There are also three patches CCd to stable to fix a but in the i965 cross-stage NIR linking which, as as side-effect, expose a nice brw_nir_link_shaders helper that we can use in anv. The bulk of the series, however, is the annoying refactoring of anv_pipeline.c to let us work with and cache the shaders an entire pipeline at a time instead of having everything be per-stage. The patch to actually add the NIR link optimizations to ANV is almost trivial. On my thermally throttled (and therefore a bit inconsistent) laptop, this seems to help the Aztec Ruins benchmark by 2%. </blockquote><div> </div><div>Or not... I'm having trouble reproducing it now. </div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> Carl Worth (1): intel/compiler: add new field for storing program size Jason Ekstrand (17): anv/pipeline: Rework the parameters to populate_wm_prog_key anv/pipeline: Add populate_tcs/tes_key helpers anv/pipline: Add a helper struct for per-stage info anv/pipeline: Populate keys up-front anv/pipeline: Hash the entire pipeline in one go anv/pipeline: Call anv_pipeline_compile_* in a loop anv/pipeline: Pull shader compilation out into a helper. anv/pipeline: Drop anv_pipeline_add_compiled_stage anv/pipeline: Recompile all shaders if any are missing from the cache anv/pipeline: Compile to NIR in compile_graphics anv/pipeline: Add a separate "link" stage anv/pipeline: Pull most of the anv_pipeline_compile_* into common code intel/nir: Add a helper for getting the NoIndirect mask intel/nir: Break the linking code into a helper in brw_nir.c intel/nir: Use the correct indirect lowering masks in link_shaders nir/lower_indirect: Bail early if modes == 0 anv/pipeline: Do cross-stage linking optimizations Jordan Justen (3): intel/compiler: Add union types for prog_data and prog_key stages intel/compiler: Add functions to get prog_data and prog_key sizes for a stage intel/compiler: Remove final_program_size from brw_compile_* src/compiler/nir/nir_lower_indirect_derefs.c | 3 + src/intel/blorp/blorp.c | 10 +- src/intel/blorp/blorp_blit.c | 5 +- src/intel/blorp/blorp_clear.c | 15 +- src/intel/blorp/blorp_priv.h | 6 +- src/intel/compiler/brw_compiler.c | 36 + src/intel/compiler/brw_compiler.h | 34 +- src/intel/compiler/brw_fs.cpp | 6 +- src/intel/compiler/brw_nir.c | 63 +- src/intel/compiler/brw_nir.h | 4 + src/intel/compiler/brw_shader.cpp | 12 +- src/intel/compiler/brw_vec4.cpp | 5 +- src/intel/compiler/brw_vec4_gs_visitor.cpp | 8 +- src/intel/compiler/brw_vec4_tcs.cpp | 12 +- src/intel/vulkan/anv_pipeline.c | 971 ++++++++++++++------------- src/intel/vulkan/anv_private.h | 2 +- src/intel/vulkan/genX_pipeline.c | 2 - src/mesa/drivers/dri/i965/brw_cs.c | 5 +- src/mesa/drivers/dri/i965/brw_gs.c | 5 +- src/mesa/drivers/dri/i965/brw_link.cpp | 38 +- src/mesa/drivers/dri/i965/brw_tcs.c | 5 +- src/mesa/drivers/dri/i965/brw_tes.c | 5 +- src/mesa/drivers/dri/i965/brw_vs.c | 11 +- src/mesa/drivers/dri/i965/brw_wm.c | 5 +- 24 files changed, 668 insertions(+), 600 deletions(-) -- 2.5.0.400.gff86faf </blockquote></div> </div></div>