<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo <<a href="mailto:jmcasanova@igalia.com" target="_blank">jmcasanova@igalia.com</a>> wrote: <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">--- src/intel/compiler/brw_eu.h | 7 +++++ src/intel/compiler/brw_eu_defines.h | 2 ++ src/intel/compiler/brw_eu_emit.c | 41 ++++++++++++++++++++++++++ src/intel/compiler/brw_fs.cpp | 10 +++++++ src/intel/compiler/brw_fs_copy_propagation.cpp | 2 ++ src/intel/compiler/brw_fs_generator.cpp | 5 ++++ src/intel/compiler/brw_fs_surface_builder.cpp | 12 ++++++++ src/intel/compiler/brw_fs_surface_builder.h | 5 ++++ src/intel/compiler/brw_shader.cpp | 6 ++++ 9 files changed, 90 insertions(+) diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index b44ca0f518..ca1ff21a83 100644 --- a/src/intel/compiler/brw_eu.h +++ b/src/intel/compiler/brw_eu.h @@ -476,6 +476,13 @@ brw_typed_surface_write(struct brw_codegen *p, unsigned num_channels); void +brw_byte_scattered_read(struct brw_codegen *p, + struct brw_reg dst, + struct brw_reg payload, + struct brw_reg surface, + unsigned msg_length); + +void brw_byte_scattered_write(struct brw_codegen *p, struct brw_reg payload, struct brw_reg surface, diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 9aac385ba7..c5dc5fd5fb 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -397,6 +397,8 @@ enum opcode { * opcode, but instead of taking a single payload blog they expect their * arguments separately as individual sources, like untyped write/read. */ + SHADER_OPCODE_BYTE_SCATTERED_READ, + SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, SHADER_OPCODE_BYTE_SCATTERED_WRITE, SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 84d85be653..8c83d8b500 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -2929,6 +2929,47 @@ brw_untyped_surface_write(struct brw_codegen *p, p, insn, num_channels); } + + +static void +brw_set_dp_byte_scattered_read_message(struct brw_codegen *p, + struct brw_inst *insn) +{ + + const struct gen_device_info *devinfo = p->devinfo; + /* Set mask of 32-bit channels to drop. */ + unsigned msg_control = GEN7_BYTE_SCATTERED_DATA_SIZE_WORD << 2; + + if (brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1) { + if (brw_inst_exec_size(devinfo, p->current) == BRW_EXECUTE_16) + msg_control |= 1; /* SIMD16 mode */ + else + msg_control |= 2; /* SIMD8 mode */ </blockquote><div> </div><div>Is this really supposed to be 2? From my reading of the BDW docs, it looks like you want 1 and 0. 2 gives you 0 in the SIMD mode bit (which indicates SIMD8) and a 1 in a reserved MBZ bit. </div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> + } </blockquote><div> </div><div>I think we probably want an else unreachable here. Also, we want that for scattered_write. </div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> + + brw_inst_set_dp_msg_type(devinfo, insn, + (devinfo->gen >= 8 || devinfo->is_haswell ? + HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ : + GEN7_DATAPORT_DC_BYTE_SCATTERED_READ)); + brw_inst_set_dp_msg_control(devinfo, insn, msg_control); +} + +void +brw_byte_scattered_read(struct brw_codegen *p, + struct brw_reg dst, + struct brw_reg payload, + struct brw_reg surface, + unsigned msg_length) +{ + const unsigned sfid = GEN7_SFID_DATAPORT_DATA_CACHE; + struct brw_inst *insn = brw_send_indirect_scattered_message( + p, sfid, dst, payload, surface, msg_length, + brw_surface_payload_size(p, 1, true, true), + false); + + brw_set_dp_byte_scattered_read_message(p, insn); </blockquote><div> </div><div>Again, I think we can inline this </div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> +} + static void brw_set_dp_byte_scattered_write(struct brw_codegen *p, struct brw_inst *insn) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index e4a94ff053..bd0d32b741 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -251,6 +251,7 @@ fs_inst::is_send_from_grf() const case SHADER_OPCODE_UNTYPED_SURFACE_READ: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: case SHADER_OPCODE_BYTE_SCATTERED_WRITE: + case SHADER_OPCODE_BYTE_SCATTERED_READ: case SHADER_OPCODE_TYPED_ATOMIC: case SHADER_OPCODE_TYPED_SURFACE_READ: case SHADER_OPCODE_TYPED_SURFACE_WRITE: @@ -733,6 +734,7 @@ fs_inst::components_read(unsigned i) const case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: + case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: assert(src[3].file == IMM); /* Surface coordinates. */ if (i == 0) @@ -800,6 +802,7 @@ fs_inst::size_read(int arg) const case SHADER_OPCODE_TYPED_SURFACE_WRITE: case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: case SHADER_OPCODE_BYTE_SCATTERED_WRITE: + case SHADER_OPCODE_BYTE_SCATTERED_READ: if (arg == 0) return mlen * REG_SIZE; break; @@ -4527,6 +4530,12 @@ fs_visitor::lower_logical_sends() ibld.sample_mask_reg()); break; + case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + lower_surface_logical_send(ibld, inst, + SHADER_OPCODE_BYTE_SCATTERED_READ, + fs_reg()); + break; + case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: lower_surface_logical_send(ibld, inst, SHADER_OPCODE_BYTE_SCATTERED_WRITE, @@ -5018,6 +5027,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo, case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: + case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: return MIN2(16, inst->exec_size); case SHADER_OPCODE_URB_READ_SIMD8: diff --git a/src/intel/compiler/brw_fs_copy_propagation.cpp b/src/intel/compiler/brw_fs_copy_propagation.cpp index fcf4706b7a..d4d01d783c 100644 --- a/src/intel/compiler/brw_fs_copy_propagation.cpp +++ b/src/intel/compiler/brw_fs_copy_propagation.cpp @@ -656,6 +656,7 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry) case SHADER_OPCODE_TYPED_SURFACE_READ: case SHADER_OPCODE_TYPED_SURFACE_WRITE: case SHADER_OPCODE_BYTE_SCATTERED_WRITE: + case SHADER_OPCODE_BYTE_SCATTERED_READ: /* We only propagate into the surface argument of the * instruction. Everything else goes through LOAD_PAYLOAD. */ @@ -696,6 +697,7 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry) case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: + case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: inst->src[i] = val; progress = true; break; diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 414da81287..c644524501 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -2053,6 +2053,11 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) inst->mlen, src[2].ud); break; + case SHADER_OPCODE_BYTE_SCATTERED_READ: + assert(src[2].file == BRW_IMMEDIATE_VALUE); + brw_byte_scattered_read(p, dst, src[0], src[1], inst->mlen); + break; + case SHADER_OPCODE_BYTE_SCATTERED_WRITE: assert(src[2].file == BRW_IMMEDIATE_VALUE); brw_byte_scattered_write(p, src[0], src[1], inst->mlen); diff --git a/src/intel/compiler/brw_fs_surface_builder.cpp b/src/intel/compiler/brw_fs_surface_builder.cpp index 5f529e9489..2b5c21fe46 100644 --- a/src/intel/compiler/brw_fs_surface_builder.cpp +++ b/src/intel/compiler/brw_fs_surface_builder.cpp @@ -1207,5 +1207,17 @@ namespace brw { addr, src, surface, dims, size, 0, pred); } + fs_reg + emit_byte_scattered_read(const fs_builder &bld, + const fs_reg &surface, const fs_reg &addr, + unsigned dims, unsigned size, + brw_predicate pred) + { + using namespace surface_access; + + return emit_send(bld, SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, + addr, fs_reg(), surface, dims, size, size, pred); + } + } } diff --git a/src/intel/compiler/brw_fs_surface_builder.h b/src/intel/compiler/brw_fs_surface_builder.h index 913ffaee72..4e62433c64 100644 --- a/src/intel/compiler/brw_fs_surface_builder.h +++ b/src/intel/compiler/brw_fs_surface_builder.h @@ -91,6 +91,11 @@ namespace brw { const fs_reg &addr, const fs_reg &src, unsigned dims, unsigned size, brw_predicate pred = BRW_PREDICATE_NONE); + fs_reg + emit_byte_scattered_read(const fs_builder &bld, + const fs_reg &surface, const fs_reg &addr, + unsigned dims, unsigned size, + brw_predicate pred = BRW_PREDICATE_NONE); } } diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index ebaf586df4..69df84ec73 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -297,6 +297,10 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op) case SHADER_OPCODE_MEMORY_FENCE: return "memory_fence"; + case SHADER_OPCODE_BYTE_SCATTERED_READ: + return "byte_scattered_read"; + case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + return "byte_scattered_read_logical"; case SHADER_OPCODE_BYTE_SCATTERED_WRITE: return "byte_scattered_write"; case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: @@ -1029,6 +1033,8 @@ backend_instruction::is_volatile() const case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_TYPED_SURFACE_READ: case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: + case SHADER_OPCODE_BYTE_SCATTERED_READ: + case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: case SHADER_OPCODE_URB_READ_SIMD8: case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT: case VEC4_OPCODE_URB_READ: -- 2.13.6 _______________________________________________ mesa-dev mailing list <a href="mailto:mesa-dev@lists.freedesktop.org">mesa-dev@lists.freedesktop.org</a> <a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev" rel="noreferrer" target="_blank">https://lists.freedesktop.org/mailman/listinfo/mesa-dev</a> </blockquote></div> </div></div>