<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Wed, Nov 29, 2017 at 6:50 PM, Jose Maria Casanova Crespo <span dir="ltr"><<a href="mailto:jmcasanova@igalia.com" target="_blank">jmcasanova@igalia.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">v2: Fix alignment style (Topi Pohjolainen)<br>
(Jason Ekstrand)<br>
- Enable bit_size parameter to scattered messages to enable different<br>
bitsizes byte/word/dword.<br>
- Remove use of brw_send_indirect_scattered_<wbr>message in favor of<br>
brw_send_indirect_surface_<wbr>message.<br>
- Move scattered messages to surface messages namespace.<br>
- Assert align1 for scattered messages and assume Gen8+.<br>
- Inline brw_set_dp_byte_scattered_<wbr>read.<br>
---<br>
src/intel/compiler/brw_eu.h | 8 +++++++<br>
src/intel/compiler/brw_eu_<wbr>defines.h | 2 ++<br>
src/intel/compiler/brw_eu_<wbr>emit.c | 30 ++++++++++++++++++++++++++<br>
src/intel/compiler/brw_fs.cpp | 19 ++++++++++++++++<br>
src/intel/compiler/brw_fs_<wbr>copy_propagation.cpp | 2 ++<br>
src/intel/compiler/brw_fs_<wbr>generator.cpp | 6 ++++++<br>
src/intel/compiler/brw_fs_<wbr>surface_builder.cpp | 11 +++++++++-<br>
src/intel/compiler/brw_fs_<wbr>surface_builder.h | 7 ++++++<br>
src/intel/compiler/brw_shader.<wbr>cpp | 6 ++++++<br>
9 files changed, 90 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h<br>
index 3ac3b4342a..2d0f56f793 100644<br>
--- a/src/intel/compiler/brw_eu.h<br>
+++ b/src/intel/compiler/brw_eu.h<br>
@@ -485,6 +485,14 @@ brw_typed_surface_write(struct brw_codegen *p,<br>
unsigned msg_length,<br>
unsigned num_channels);<br>
<br>
+void<br>
+brw_byte_scattered_read(<wbr>struct brw_codegen *p,<br>
+ struct brw_reg dst,<br>
+ struct brw_reg payload,<br>
+ struct brw_reg surface,<br>
+ unsigned msg_length,<br>
+ unsigned bit_size);<br>
+<br>
void<br>
brw_byte_scattered_write(<wbr>struct brw_codegen *p,<br>
struct brw_reg payload,<br>
diff --git a/src/intel/compiler/brw_eu_<wbr>defines.h b/src/intel/compiler/brw_eu_<wbr>defines.h<br>
index de6330ee54..aa510ebfa4 100644<br>
--- a/src/intel/compiler/brw_eu_<wbr>defines.h<br>
+++ b/src/intel/compiler/brw_eu_<wbr>defines.h<br>
@@ -409,6 +409,8 @@ enum opcode {<br>
* opcode, but instead of taking a single payload blog they expect their<br>
* arguments separately as individual sources, like untyped write/read.<br>
*/<br>
+ SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ,<br>
+ SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ_LOGICAL,<br>
SHADER_OPCODE_BYTE_SCATTERED_<wbr>WRITE,<br>
SHADER_OPCODE_BYTE_SCATTERED_<wbr>WRITE_LOGICAL,<br>
<br>
diff --git a/src/intel/compiler/brw_eu_<wbr>emit.c b/src/intel/compiler/brw_eu_<wbr>emit.c<br>
index ded7e228cf..bdc516848a 100644<br>
--- a/src/intel/compiler/brw_eu_<wbr>emit.c<br>
+++ b/src/intel/compiler/brw_eu_<wbr>emit.c<br>
@@ -2998,6 +2998,36 @@ static enum brw_data_size brw_data_size_from_bit_size(<wbr>unsigned bit_size)<br>
}<br>
}<br>
<br>
+<br>
+void<br>
+brw_byte_scattered_read(<wbr>struct brw_codegen *p,<br>
+ struct brw_reg dst,<br>
+ struct brw_reg payload,<br>
+ struct brw_reg surface,<br>
+ unsigned msg_length,<br>
+ unsigned bit_size)<br>
+{<br>
+ assert(brw_inst_access_mode(p-<wbr>>devinfo, p->current) == BRW_ALIGN_1);<br>
+ const struct gen_device_info *devinfo = p->devinfo;<br>
+ const unsigned sfid = GEN7_SFID_DATAPORT_DATA_CACHE;<br>
+<br>
+ struct brw_inst *insn = brw_send_indirect_surface_<wbr>message(<br>
+ p, sfid, dst, payload, surface, msg_length,<br>
+ brw_surface_payload_size(p, 1, true, true),<br>
+ false);<br>
+<br>
+ unsigned msg_control = brw_data_size_from_bit_size(<wbr>bit_size) << 2;<br>
+<br>
+ if (brw_inst_exec_size(devinfo, p->current) == BRW_EXECUTE_16)<br>
+ msg_control |= 1; /* SIMD16 mode */<br>
+ else<br>
+ msg_control |= 0; /* SIMD8 mode */<br>
+<br>
+ brw_inst_set_dp_msg_type(<wbr>devinfo, insn,<br>
+ HSW_DATAPORT_DC_PORT0_BYTE_<wbr>SCATTERED_READ);<br>
+ brw_inst_set_dp_msg_control(<wbr>devinfo, insn, msg_control);<br>
+}<br>
+<br>
void<br>
brw_byte_scattered_write(<wbr>struct brw_codegen *p,<br>
struct brw_reg payload,<br>
diff --git a/src/intel/compiler/brw_fs.<wbr>cpp b/src/intel/compiler/brw_fs.<wbr>cpp<br>
index 32f1d757f0..1ca4d416b2 100644<br>
--- a/src/intel/compiler/brw_fs.<wbr>cpp<br>
+++ b/src/intel/compiler/brw_fs.<wbr>cpp<br>
@@ -251,6 +251,7 @@ fs_inst::is_send_from_grf() const<br>
case SHADER_OPCODE_UNTYPED_SURFACE_<wbr>READ:<br>
case SHADER_OPCODE_UNTYPED_SURFACE_<wbr>WRITE:<br>
case SHADER_OPCODE_BYTE_SCATTERED_<wbr>WRITE:<br>
+ case SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ:<br>
case SHADER_OPCODE_TYPED_ATOMIC:<br>
case SHADER_OPCODE_TYPED_SURFACE_<wbr>READ:<br>
case SHADER_OPCODE_TYPED_SURFACE_<wbr>WRITE:<br>
@@ -750,6 +751,16 @@ fs_inst::components_read(<wbr>unsigned i) const<br>
else<br>
return 1;<br>
<br>
+ case SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ_LOGICAL:<br>
+ assert(src[3].file == IMM &&<br>
+ src[4].file == IMM);<br>
+ if (i == 0)<br>
+ return 1;<br>
+ else if (i == 1)<br>
+ return 0;<br></blockquote><div><br></div><div>I suppose src[1] is for the data to write which is unused for this opcode? If so, I'd rather we just do</div><div><br></div><div>/* src[1] is normally for data to write and is unused */</div><div>return i == 1 ? 0 : 1;<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+ else<br>
+ return 1;<br>
+<br>
case SHADER_OPCODE_BYTE_SCATTERED_<wbr>WRITE_LOGICAL:<br>
assert(src[3].file == IMM &&<br>
src[4].file == IMM);<br>
@@ -798,6 +809,7 @@ fs_inst::size_read(int arg) const<br>
case SHADER_OPCODE_TYPED_SURFACE_<wbr>WRITE:<br>
case FS_OPCODE_INTERPOLATE_AT_PER_<wbr>SLOT_OFFSET:<br>
case SHADER_OPCODE_BYTE_SCATTERED_<wbr>WRITE:<br>
+ case SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ:<br>
if (arg == 0)<br>
return mlen * REG_SIZE;<br>
break;<br>
@@ -4545,6 +4557,12 @@ fs_visitor::lower_logical_<wbr>sends()<br>
ibld.sample_mask_reg());<br>
break;<br>
<br>
+ case SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ_LOGICAL:<br>
+ lower_surface_logical_send(<wbr>ibld, inst,<br>
+ SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ,<br>
+ fs_reg());<br>
+ break;<br>
+<br>
case SHADER_OPCODE_BYTE_SCATTERED_<wbr>WRITE_LOGICAL:<br>
lower_surface_logical_send(<wbr>ibld, inst,<br>
SHADER_OPCODE_BYTE_SCATTERED_<wbr>WRITE,<br>
@@ -5036,6 +5054,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,<br>
case SHADER_OPCODE_UNTYPED_SURFACE_<wbr>READ_LOGICAL:<br>
case SHADER_OPCODE_UNTYPED_SURFACE_<wbr>WRITE_LOGICAL:<br>
case SHADER_OPCODE_BYTE_SCATTERED_<wbr>WRITE_LOGICAL:<br>
+ case SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ_LOGICAL:<br>
return MIN2(16, inst->exec_size);<br>
<br>
case SHADER_OPCODE_URB_READ_SIMD8:<br>
diff --git a/src/intel/compiler/brw_fs_<wbr>copy_propagation.cpp b/src/intel/compiler/brw_fs_<wbr>copy_propagation.cpp<br>
index fcf4706b7a..d4d01d783c 100644<br>
--- a/src/intel/compiler/brw_fs_<wbr>copy_propagation.cpp<br>
+++ b/src/intel/compiler/brw_fs_<wbr>copy_propagation.cpp<br>
@@ -656,6 +656,7 @@ fs_visitor::try_constant_<wbr>propagate(fs_inst *inst, acp_entry *entry)<br>
case SHADER_OPCODE_TYPED_SURFACE_<wbr>READ:<br>
case SHADER_OPCODE_TYPED_SURFACE_<wbr>WRITE:<br>
case SHADER_OPCODE_BYTE_SCATTERED_<wbr>WRITE:<br>
+ case SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ:<br>
/* We only propagate into the surface argument of the<br>
* instruction. Everything else goes through LOAD_PAYLOAD.<br>
*/<br>
@@ -696,6 +697,7 @@ fs_visitor::try_constant_<wbr>propagate(fs_inst *inst, acp_entry *entry)<br>
case SHADER_OPCODE_TYPED_SURFACE_<wbr>READ_LOGICAL:<br>
case SHADER_OPCODE_TYPED_SURFACE_<wbr>WRITE_LOGICAL:<br>
case SHADER_OPCODE_BYTE_SCATTERED_<wbr>WRITE_LOGICAL:<br>
+ case SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ_LOGICAL:<br>
inst->src[i] = val;<br>
progress = true;<br>
break;<br>
diff --git a/src/intel/compiler/brw_fs_<wbr>generator.cpp b/src/intel/compiler/brw_fs_<wbr>generator.cpp<br>
index fedc9acf97..a3861cd68e 100644<br>
--- a/src/intel/compiler/brw_fs_<wbr>generator.cpp<br>
+++ b/src/intel/compiler/brw_fs_<wbr>generator.cpp<br>
@@ -2073,6 +2073,12 @@ fs_generator::generate_code(<wbr>const cfg_t *cfg, int dispatch_width)<br>
inst->mlen, src[2].ud);<br>
break;<br>
<br>
+ case SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ:<br>
+ assert(src[2].file == BRW_IMMEDIATE_VALUE);<br>
+ brw_byte_scattered_read(p, dst, src[0], src[1],<br>
+ inst->mlen, src[2].ud);<br>
+ break;<br>
+<br>
case SHADER_OPCODE_BYTE_SCATTERED_<wbr>WRITE:<br>
assert(src[2].file == BRW_IMMEDIATE_VALUE);<br>
brw_byte_scattered_write(p, src[0], src[1],<br>
diff --git a/src/intel/compiler/brw_fs_<wbr>surface_builder.cpp b/src/intel/compiler/brw_fs_<wbr>surface_builder.cpp<br>
index 37cc29e361..c346ef9e70 100644<br>
--- a/src/intel/compiler/brw_fs_<wbr>surface_builder.cpp<br>
+++ b/src/intel/compiler/brw_fs_<wbr>surface_builder.cpp<br>
@@ -161,6 +161,16 @@ namespace brw {<br>
addr, tmp, surface, dims, op, rsize);<br>
}<br>
<br>
+ fs_reg<br>
+ emit_byte_scattered_read(const fs_builder &bld,<br>
+ const fs_reg &surface, const fs_reg &addr,<br>
+ unsigned dims, unsigned size,<br>
+ unsigned bit_size, brw_predicate pred)<br>
+ {<br>
+ return emit_send(bld, SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ_LOGICAL,<br>
+ addr, fs_reg(), surface, dims, bit_size, size, pred);<br>
+ }<br>
+<br>
void<br>
emit_byte_scattered_write(<wbr>const fs_builder &bld, const fs_reg &surface,<br>
const fs_reg &addr, const fs_reg &src,<br>
@@ -1202,4 +1212,3 @@ namespace brw {<br>
}<br>
}<br>
}<br>
-<br>
diff --git a/src/intel/compiler/brw_fs_<wbr>surface_builder.h b/src/intel/compiler/brw_fs_<wbr>surface_builder.h<br>
index bf9a8c68c8..194d61d489 100644<br>
--- a/src/intel/compiler/brw_fs_<wbr>surface_builder.h<br>
+++ b/src/intel/compiler/brw_fs_<wbr>surface_builder.h<br>
@@ -64,6 +64,13 @@ namespace brw {<br>
unsigned dims, unsigned rsize, unsigned op,<br>
brw_predicate pred = BRW_PREDICATE_NONE);<br>
<br>
+ fs_reg<br>
+ emit_byte_scattered_read(const fs_builder &bld,<br>
+ const fs_reg &surface, const fs_reg &addr,<br>
+ unsigned dims, unsigned size,<br>
+ unsigned bit_size,<br>
+ brw_predicate pred = BRW_PREDICATE_NONE);<br>
+<br>
void<br>
emit_byte_scattered_write(<wbr>const fs_builder &bld, const fs_reg &surface,<br>
const fs_reg &addr, const fs_reg &src,<br>
diff --git a/src/intel/compiler/brw_<wbr>shader.cpp b/src/intel/compiler/brw_<wbr>shader.cpp<br>
index 209552e1b2..74b52976d7 100644<br>
--- a/src/intel/compiler/brw_<wbr>shader.cpp<br>
+++ b/src/intel/compiler/brw_<wbr>shader.cpp<br>
@@ -293,6 +293,10 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)<br>
case SHADER_OPCODE_MEMORY_FENCE:<br>
return "memory_fence";<br>
<br>
+ case SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ:<br>
+ return "byte_scattered_read";<br>
+ case SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ_LOGICAL:<br>
+ return "byte_scattered_read_logical";<br>
case SHADER_OPCODE_BYTE_SCATTERED_<wbr>WRITE:<br>
return "byte_scattered_write";<br>
case SHADER_OPCODE_BYTE_SCATTERED_<wbr>WRITE_LOGICAL:<br>
@@ -999,6 +1003,8 @@ backend_instruction::is_<wbr>volatile() const<br>
case SHADER_OPCODE_UNTYPED_SURFACE_<wbr>READ_LOGICAL:<br>
case SHADER_OPCODE_TYPED_SURFACE_<wbr>READ:<br>
case SHADER_OPCODE_TYPED_SURFACE_<wbr>READ_LOGICAL:<br>
+ case SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ:<br>
+ case SHADER_OPCODE_BYTE_SCATTERED_<wbr>READ_LOGICAL:<br>
case SHADER_OPCODE_URB_READ_SIMD8:<br>
case SHADER_OPCODE_URB_READ_SIMD8_<wbr>PER_SLOT:<br>
case VEC4_OPCODE_URB_READ:<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.14.3<br>
<br>
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</font></span></blockquote></div><br></div></div>