<div dir="ltr"><div>Please put this one somewhere before we turn the extension on in anv as it's needed for correctness.<br><br></div>Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a><br><div><div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Nov 29, 2017 at 6:57 PM, Jose Maria Casanova Crespo <span dir="ltr"><<a href="mailto:jmcasanova@igalia.com" target="_blank">jmcasanova@igalia.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Alejandro Piñeiro <<a href="mailto:apinheiro@igalia.com">apinheiro@igalia.com</a>><br>
<br>
While on Untyped Surface messages the bits of the execution mask are<br>
ANDed with the corresponding bits of the Pixel/Sample Mask, that is<br>
not the case for byte scattered writes. That is needed to avoid ssbo<br>
stores writing on helper invocations. So when that can affect, we load<br>
the sample mask, and predicate the send message.<br>
<br>
Note: the need for this patch was tested with a custom test. Right now<br>
the 16 bit storage CTS tests doesnt need this path in order to get a<br>
full pass.<br></blockquote><div><br></div><div>Is that a CTS test, crucible test, or something else? It would be good to get it landed into some upstream test suite.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
---<br>
src/intel/compiler/brw_fs_nir.<wbr>cpp | 14 +++++++++++++-<br>
1 file changed, 13 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/src/intel/compiler/brw_fs_<wbr>nir.cpp b/src/intel/compiler/brw_fs_<wbr>nir.cpp<br>
index 2c344ec7df..fa7aa9c247 100644<br>
--- a/src/intel/compiler/brw_fs_<wbr>nir.cpp<br>
+++ b/src/intel/compiler/brw_fs_<wbr>nir.cpp<br>
@@ -4167,12 +4167,24 @@ fs_visitor::nir_emit_<wbr>intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr<br>
* to rely on byte scattered in order to write 16-bit elements.<br>
* The byte_scattered_write message needs that every written 16-bit<br>
* type to be aligned 32-bits (stride=2).<br>
+ * Additionally, while on Untyped Surface messages the<br>
+ * bits of the execution mask are ANDed with the corresponding<br>
+ * bits of the Pixel/Sample Mask, that is not the case for byte<br>
+ * scattered writes. That is needed to avoid ssbo stores writing<br>
+ * on helper invocations. So when that can affect, we load the<br>
+ * sample mask, and predicate the send message.<br>
*/<br>
+ brw_predicate pred = BRW_PREDICATE_NONE;<br>
+<br>
+ if (stage == MESA_SHADER_FRAGMENT) {<br>
+ bld.emit(FS_OPCODE_MOV_<wbr>DISPATCH_TO_FLAGS);<br>
+ pred = BRW_PREDICATE_NORMAL;<br>
+ }<br>
emit_byte_scattered_write(bld, surf_index, offset_reg,<br>
current_val_reg,<br>
1 /* dims */, 1,<br>
bit_size,<br>
- BRW_PREDICATE_NONE);<br>
+ pred);<br>
} else {<br>
unsigned write_size = (length * type_size) / 4;<br>
assert (write_size > 0);<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.14.3<br>
<br>
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</font></span></blockquote></div><br></div></div></div></div>