<div dir="ltr">I don't think we can do this either, as the indirect draw packets require a group of 2 SGPRs to put them in, even if you don't use them.</div><div class="gmail_extra"> <div class="gmail_quote">On Mon, Jan 29, 2018 at 12:40 PM, Samuel Pitoiset <<a href="mailto:samuel.pitoiset@gmail.com" target="_blank">samuel.pitoiset@gmail.com</a>> wrote: <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">This should reduce the number of emitted SH_REG packets. Signed-off-by: Samuel Pitoiset <<a href="mailto:samuel.pitoiset@gmail.com">samuel.pitoiset@gmail.com</a>> --- src/amd/common/ac_nir_to_llvm.c | 23 +++++++++++++++++++---- src/amd/vulkan/radv_cmd_buffer.c | 27 +++++++++++++++++---------- src/amd/vulkan/radv_pipeline.c | 11 +++++++++++ src/amd/vulkan/radv_private.h | 1 + 4 files changed, 48 insertions(+), 14 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 47f62f42dc..34133b8d23 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -655,8 +655,14 @@ declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx, add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32), &ctx->vertex_buffers); } - add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex); - add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance); + + if (ctx->shader_info->info.vs.needs_base_vertex) { + add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex); + } + + if (ctx->shader_info->info.vs.needs_start_instance) { + add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance); + } } } @@ -737,13 +743,22 @@ set_vs_specific_input_locs(struct nir_to_llvm_context *ctx, if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) { + uint8_t num_sgprs = 0; + if (ctx->shader_info->info.vs.has_vertex_buffers) { set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2); } - set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, - user_sgpr_idx, 2); + if (ctx->shader_info->info.vs.needs_base_vertex) + num_sgprs++; + if (ctx->shader_info->info.vs.needs_start_instance) + num_sgprs++; + + if (num_sgprs > 0) { + set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, + user_sgpr_idx, num_sgprs); + } } } diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index e347c3f563..ccfafe8b58 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3356,17 +3356,24 @@ radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer, } } } else { - assert(state->pipeline->graphics.vtx_base_sgpr); - - if (info->vertex_offset != state->last_vertex_offset || - info->first_instance != state->last_first_instance) { - radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr, 2); - - radeon_emit(cs, info->vertex_offset); - radeon_emit(cs, info->first_instance); + if (state->pipeline->graphics.vtx_base_sgpr && + (info->vertex_offset != state->last_vertex_offset || + info->first_instance != state->last_first_instance)) { + struct radv_shader_variant *vs = + radv_get_vertex_shader(state->pipeline); + + radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr, + state->pipeline->graphics.vtx_emit_num); + + if (vs->info.info.vs.needs_base_vertex) { + radeon_emit(cs, info->vertex_offset); + state->last_vertex_offset = info->vertex_offset; + } - state->last_first_instance = info->first_instance; - state->last_vertex_offset = info->vertex_offset; + if (vs->info.info.vs.needs_start_instance) { + radeon_emit(cs, info->first_instance); + state->last_first_instance = info->first_instance; + } } if (state->last_num_instances != info->instance_count) { diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index a3ba6ee3aa..38b6be683d 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2689,8 +2689,19 @@ radv_pipeline_init(struct radv_pipeline *pipeline, struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_BASE_VERTEX_START_INSTANCE); if (loc->sgpr_idx != -1) { + struct radv_shader_variant *vs = + radv_get_vertex_shader(pipeline); + uint8_t num_sgprs = 0; + pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX]; pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4; + + if (vs->info.info.vs.needs_base_vertex) + num_sgprs++; + if (vs->info.info.vs.needs_start_instance) + num_sgprs++; + + pipeline->graphics.vtx_emit_num = num_sgprs; } pipeline->graphics.vtx_reuse_depth = 30; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 7ad0c3baa8..f650b9a360 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1257,6 +1257,7 @@ struct radv_pipeline { bool wd_switch_on_eop; bool ia_switch_on_eoi; bool partial_vs_wave; + uint8_t vtx_emit_num; uint32_t vtx_reuse_depth; struct radv_prim_vertex_count prim_vertex_count; bool can_use_guardband; -- 2.16.1 _______________________________________________ mesa-dev mailing list <a href="mailto:mesa-dev@lists.freedesktop.org">mesa-dev@lists.freedesktop.org</a> <a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev" rel="noreferrer" target="_blank">https://lists.freedesktop.org/mailman/listinfo/mesa-dev</a> </blockquote></div> </div>