<div dir="ltr"><div><div>If you rename the function in patch 10, patches 10-14 are:<br><br></div>Reviewed-by: Marek Olšák <<a href="mailto:marek.olsak@amd.com">marek.olsak@amd.com</a>><br><br></div>Marek<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Mar 14, 2018 at 2:01 AM, Timothy Arceri <span dir="ltr"><<a href="mailto:tarceri@itsqueeze.com" target="_blank">tarceri@itsqueeze.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">---<br>
src/gallium/drivers/radeonsi/<wbr>si_get.c | 6 +++++-<br>
src/mesa/state_tracker/st_<wbr>glsl_to_nir.cpp | 10 ++--------<br>
2 files changed, 7 insertions(+), 9 deletions(-)<br>
<br>
diff --git a/src/gallium/drivers/<wbr>radeonsi/si_get.c b/src/gallium/drivers/<wbr>radeonsi/si_get.c<br>
index 323700d425..b4ca5bea94 100644<br>
--- a/src/gallium/drivers/<wbr>radeonsi/si_get.c<br>
+++ b/src/gallium/drivers/<wbr>radeonsi/si_get.c<br>
@@ -251,6 +251,11 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)<br>
return RADEON_SPARSE_PAGE_SIZE;<br>
return 0;<br>
<br>
+ case PIPE_CAP_PACKED_UNIFORMS:<br>
+ if (sscreen->debug_flags & DBG(NIR))<br>
+ return 1;<br>
+ return 0;<br>
+<br>
/* Unsupported features. */<br>
case PIPE_CAP_BUFFER_SAMPLER_VIEW_<wbr>RGBA_ONLY:<br>
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_<wbr>LOWER_LEFT:<br>
@@ -269,7 +274,6 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)<br>
case PIPE_CAP_TILE_RASTER_ORDER:<br>
case PIPE_CAP_MAX_COMBINED_SHADER_<wbr>OUTPUT_RESOURCES:<br>
case PIPE_CAP_CONTEXT_PRIORITY_<wbr>MASK:<br>
- case PIPE_CAP_PACKED_UNIFORMS:<br>
return 0;<br>
<br>
case PIPE_CAP_FENCE_SIGNAL:<br>
diff --git a/src/mesa/state_tracker/st_<wbr>glsl_to_nir.cpp b/src/mesa/state_tracker/st_<wbr>glsl_to_nir.cpp<br>
index 9006650517..49f9fd0367 100644<br>
--- a/src/mesa/state_tracker/st_<wbr>glsl_to_nir.cpp<br>
+++ b/src/mesa/state_tracker/st_<wbr>glsl_to_nir.cpp<br>
@@ -753,14 +753,8 @@ st_finalize_nir(struct st_context *st, struct gl_program *prog,<br>
st_nir_assign_uniform_<wbr>locations(st->ctx, prog, shader_program,<br>
&nir->uniforms, &nir->num_uniforms);<br>
<br>
- /* Below is a quick hack so that uniform lowering only runs on radeonsi<br>
- * (the only NIR backend that currently supports tess) once we enable<br>
- * uniform packing support we will just use<br>
- * ctx->Const.<wbr>PackedDriverUniformStorage for this check.<br>
- */<br>
- if (screen->get_shader_param(<wbr>screen, PIPE_SHADER_TESS_CTRL,<br>
- PIPE_SHADER_CAP_MAX_<wbr>INSTRUCTIONS) > 0) {<br>
- NIR_PASS_V(nir, nir_lower_io, nir_var_uniform, type_size,<br>
+ if (st->ctx->Const.<wbr>PackedDriverUniformStorage) {<br>
+ NIR_PASS_V(nir, nir_lower_io, nir_var_uniform, st_glsl_type_size_scalar,<br>
(nir_lower_io_options)0);<br>
NIR_PASS_V(nir, st_nir_lower_uniforms_to_ubo, prog->Parameters);<br>
}<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.14.3<br>
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</font></span></blockquote></div><br></div>