<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Wed, Apr 4, 2018 at 9:01 AM, Michel Dänzer <span dir="ltr"><<a href="mailto:michel@daenzer.net" target="_blank">michel@daenzer.net</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span>On 2018-04-04 02:57 PM, Marek Olšák wrote:<br>
> On Wed, Apr 4, 2018, 6:18 AM Michel Dänzer <<a href="mailto:michel@daenzer.net" target="_blank">michel@daenzer.net</a><br>
</span><span>> <mailto:<a href="mailto:michel@daenzer.net" target="_blank">michel@daenzer.net</a>>> wrote:<br>
><br>
> On 2018-04-04 03:59 AM, Marek Olšák wrote:<br>
</span>> > From: Marek Olšák <<a href="mailto:marek.olsak@amd.com" target="_blank">marek.olsak@amd.com</a> <mailto:<a href="mailto:marek.olsak@amd.com" target="_blank">marek.olsak@amd.com</a>>><br>
<div><div class="m_2603895745529203103h5">> ><br>
> > This enables the tile swizzle for some cases of the displayable<br>
> micro mode,<br>
> > and it also fixes an addrlib assertion failure on Vega.<br>
> > ---<br>
> > src/amd/common/ac_surface.c | 18 ++++++++++++++----<br>
> > 1 file changed, 14 insertions(+), 4 deletions(-)<br>
> ><br>
> > diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c<br>
> > index b294cd85259..2b20a553d51 100644<br>
> > --- a/src/amd/common/ac_surface.c<br>
> > +++ b/src/amd/common/ac_surface.c<br>
> > @@ -408,20 +408,29 @@ static unsigned<br>
> cik_get_macro_tile_index(stru<wbr>ct radeon_surf *surf)<br>
> > tileb = 8 * 8 * surf->bpe;<br>
> > tileb = MIN2(surf->u.legacy.tile_split<wbr>, tileb);<br>
> ><br>
> > for (index = 0; tileb > 64; index++)<br>
> > tileb >>= 1;<br>
> ><br>
> > assert(index < 16);<br>
> > return index;<br>
> > }<br>
> ><br>
> > +static bool get_display_flag(const struct ac_surf_config *config,<br>
> > + const struct radeon_surf *surf)<br>
> > +{<br>
> > + return surf->flags & RADEON_SURF_SCANOUT &&<br>
> > + !(surf->flags & RADEON_SURF_FMASK) &&<br>
> > + config->info.samples <= 1 &&<br>
> > + surf->bpe >= 4 && surf->bpe <= 8;<br>
><br>
> surf->bpe is the number of bytes used to store each pixel, right? If so,<br>
> this cannot exclude surf->bpe < 4, since 16 bpp and 8 bpp formats can be<br>
> displayed.<br>
><br>
><br>
> Sure, but what are the chances they will be displayed with the current<br>
> stack? GLX doesn't have 16bpp visuals for on-screen rendering.<br>
<br>
</div></div>Maybe not when the X server runs at depth 24, but it can also run at<br>
depths 8, 15 & 16, in which case displayable surfaces with bpe == 1 or 2<br>
are needed even before GLX even comes into the picture.<br></blockquote><div><br></div><div>OK. Let me ask differently. Do we wanna support displayable 8, 15, and 16 bpp? Can we just say that we don't support those?<br><br></div><div>Marek<br></div></div></div></div>