<div dir="auto"><div><div class="gmail_quote"><div dir="ltr">On Thu, Apr 5, 2018, 3:09 AM Michel Dänzer <<a href="mailto:michel@daenzer.net">michel@daenzer.net</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">On 2018-04-04 07:35 PM, Marek Olšák wrote:<br>
> On Wed, Apr 4, 2018 at 9:01 AM, Michel Dänzer <<a href="mailto:michel@daenzer.net" target="_blank" rel="noreferrer">michel@daenzer.net</a>> wrote:<br>
>> On 2018-04-04 02:57 PM, Marek Olšák wrote:<br>
>>> On Wed, Apr 4, 2018, 6:18 AM Michel Dänzer <<a href="mailto:michel@daenzer.net" target="_blank" rel="noreferrer">michel@daenzer.net</a><br>
>>> <mailto:<a href="mailto:michel@daenzer.net" target="_blank" rel="noreferrer">michel@daenzer.net</a>>> wrote:<br>
>>><br>
>>> On 2018-04-04 03:59 AM, Marek Olšák wrote:<br>
>>> > From: Marek Olšák <<a href="mailto:marek.olsak@amd.com" target="_blank" rel="noreferrer">marek.olsak@amd.com</a> <mailto:<a href="mailto:marek.olsak@amd.com" target="_blank" rel="noreferrer">marek.olsak@amd.com</a><br>
>>>><br>
>>> ><br>
>>> > This enables the tile swizzle for some cases of the displayable<br>
>>> micro mode,<br>
>>> > and it also fixes an addrlib assertion failure on Vega.<br>
>>> > ---<br>
>>> > src/amd/common/ac_surface.c | 18 ++++++++++++++----<br>
>>> > 1 file changed, 14 insertions(+), 4 deletions(-)<br>
>>> ><br>
>>> > diff --git a/src/amd/common/ac_surface.c<br>
>> b/src/amd/common/ac_surface.c<br>
>>> > index b294cd85259..2b20a553d51 100644<br>
>>> > --- a/src/amd/common/ac_surface.c<br>
>>> > +++ b/src/amd/common/ac_surface.c<br>
>>> > @@ -408,20 +408,29 @@ static unsigned<br>
>>> cik_get_macro_tile_index(struct radeon_surf *surf)<br>
>>> > tileb = 8 * 8 * surf->bpe;<br>
>>> > tileb = MIN2(surf->u.legacy.tile_split, tileb);<br>
>>> ><br>
>>> > for (index = 0; tileb > 64; index++)<br>
>>> > tileb >>= 1;<br>
>>> ><br>
>>> > assert(index < 16);<br>
>>> > return index;<br>
>>> > }<br>
>>> ><br>
>>> > +static bool get_display_flag(const struct ac_surf_config *config,<br>
>>> > + const struct radeon_surf *surf)<br>
>>> > +{<br>
>>> > + return surf->flags & RADEON_SURF_SCANOUT &&<br>
>>> > + !(surf->flags & RADEON_SURF_FMASK) &&<br>
>>> > + config->info.samples <= 1 &&<br>
>>> > + surf->bpe >= 4 && surf->bpe <= 8;<br>
>>><br>
>>> surf->bpe is the number of bytes used to store each pixel, right? If<br>
>> so,<br>
>>> this cannot exclude surf->bpe < 4, since 16 bpp and 8 bpp formats<br>
>> can be<br>
>>> displayed.<br>
>>><br>
>>><br>
>>> Sure, but what are the chances they will be displayed with the current<br>
>>> stack? GLX doesn't have 16bpp visuals for on-screen rendering.<br>
>><br>
>> Maybe not when the X server runs at depth 24, but it can also run at<br>
>> depths 8, 15 & 16, in which case displayable surfaces with bpe == 1 or 2<br>
>> are needed even before GLX even comes into the picture.<br>
>><br>
><br>
> OK. Let me ask differently. Do we wanna support displayable 8, 15, and 16<br>
> bpp?<br>
<br>
We do support it, it's not really a question of whether we want to<br>
anymore. :)<br>
<br>
> Can we just say that we don't support those?<br>
<br>
I'm afraid we can't.<br>
<br>
<br>
Which kind of surfaces are you trying to exclude like this? Maybe they<br>
can be excluded in a different way.<br></blockquote></div></div><div dir="auto"><br></div><div dir="auto">Currently just the MSAA resolve temporary destination buffer.</div><div dir="auto"><br></div><div dir="auto">Marek</div><div dir="auto"><br></div><div dir="auto"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
<br>
--<br>
Earthling Michel Dänzer | <a href="http://www.amd.com" rel="noreferrer noreferrer" target="_blank">http://www.amd.com</a><br>
Libre software enthusiast | Mesa and X developer<br>
</blockquote></div></div></div>