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On 10/04/18 18:26, Jason Ekstrand wrote:<br>
<blockquote type="cite"
cite="mid:CAOFGe97jddBanqjPA-C7K3csebV2G1-FnuAb0tu5Q_o1DyiNvw@mail.gmail.com">
<div dir="ltr">
<div class="gmail_extra">
<div class="gmail_quote">On Tue, Apr 10, 2018 at 1:28 AM,
Antia Puentes <span dir="ltr"><<a
href="mailto:apuentes@igalia.com" target="_blank"
moz-do-not-send="true">apuentes@igalia.com</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">
<div text="#000000" bgcolor="#FFFFFF">
<div>
<div class="h5">
<p>On 07/04/18 08:21, Jason Ekstrand wrote:<br>
</p>
<blockquote type="cite">
<div dir="ltr">
<div class="gmail_extra">
<div class="gmail_quote">On Fri, Apr 6, 2018
at 2:53 PM, Ian Romanick <span dir="ltr"><<a
href="mailto:idr@freedesktop.org"
target="_blank" moz-do-not-send="true">idr@freedesktop.org</a>></span>
wrote:<br>
<blockquote class="gmail_quote"
style="margin:0 0 0 .8ex;border-left:1px
#ccc solid;padding-left:1ex">From: Antia
Puentes <<a
href="mailto:apuentes@igalia.com"
target="_blank" moz-do-not-send="true">apuentes@igalia.com</a>><br>
<br>
We keep 'firstvertex' as it is and move
gl_BaseVertex to the drawID<br>
vertex element. The previous Vertex
Elements order was:<br>
<br>
* VE 1: <BaseVertex/firstvertex,
BaseInstance, VertexID, InstanceID><br>
* VE 2: <Draw ID, 0, 0, 0><br>
<br>
and now it is:<br>
<br>
* VE 1: <firstvertex, BaseInstance,
VertexID, InstanceID><br>
* VE 2: <Draw ID, BaseVertex, 0,
0><br>
<br>
To move the BaseVertex keeping VE1 as it
is, allows to keep pointing the<br>
vertex buffer associated to VE 1 to the
indirect buffer for indirect<br>
draw calls.<br>
<br>
From the OpenGL 4.6 (11.1.3.9 Shader
Inputs) specification:<br>
<br>
"gl_BaseVertex holds the integer value
passed to the baseVertex<br>
parameter to the command that resulted
in the current shader<br>
invocation. In the case where the
command has no baseVertex parameter,<br>
the value of gl_BaseVertex is zero."<br>
<br>
Fixes CTS tests:<br>
<br>
* KHR-GL45.shader_draw_parameter<wbr>s_tests.ShaderDrawArraysParame<wbr>ters<br>
* KHR-GL45.shader_draw_parameter<wbr>s_tests.ShaderDrawArraysInstan<wbr>cedParameters<br>
* KHR-GL45.shader_draw_parameter<wbr>s_tests.ShaderMultiDrawArraysP<wbr>arameters<br>
* KHR-GL45.shader_draw_parameter<wbr>s_tests.ShaderMultiDrawArraysI<wbr>ndirectParameters<br>
* KHR-GL45.shader_draw_parameter<wbr>s_tests.MultiDrawArraysIndirec<wbr>tCountParameters<br>
<br>
v2 (idr): Make changes to
brw_prepare_shader_draw_parame<wbr>ters
matching<br>
those in genX(emit_vertices). Reformat
commit message to 72 columns.<br>
<br>
Signed-off-by: Ian Romanick <<a
href="mailto:ian.d.romanick@intel.com"
target="_blank" moz-do-not-send="true">ian.d.romanick@intel.com</a>><br>
Bugzilla: <a
href="https://bugs.freedesktop.org/show_bug.cgi?id=102678"
rel="noreferrer" target="_blank"
moz-do-not-send="true">https://bugs.freedesktop.org/s<wbr>how_bug.cgi?id=102678</a><br>
---<br>
src/intel/compiler/brw_nir.c
| 14 +++++----<br>
src/intel/compiler/brw_vec4.c<wbr>pp
| 14 +++++----<br>
src/mesa/drivers/dri/i965/<wbr>brw_context.h
| 32 ++++++++++++++-----<br>
src/mesa/drivers/dri/i965/<wbr>brw_draw.c
| 45 ++++++++++++++++++---------<br>
src/mesa/drivers/dri/i965/<wbr>brw_draw_upload.c
| 14 ++++-----<br>
src/mesa/drivers/dri/i965/gen<wbr>X_state_upload.c
| 38 +++++++++++-----------<br>
6 files changed, 97 insertions(+), 60
deletions(-)<br>
<br>
diff --git a/src/intel/compiler/brw_nir.c
b/src/intel/compiler/brw_nir.c<br>
index 16b0d86814f..16ab529737b 100644<br>
--- a/src/intel/compiler/brw_nir.c<br>
+++ b/src/intel/compiler/brw_nir.c<br>
@@ -238,8 +238,7 @@
brw_nir_lower_vs_inputs(nir_sh<wbr>ader
*nir,<br>
*/<br>
const bool has_sgvs =<br>
nir->info.system_values_read
&<br>
- (BITFIELD64_BIT(SYSTEM_VALUE_B<wbr>ASE_VERTEX)
|<br>
- BITFIELD64_BIT(SYSTEM_VALUE_F<wbr>IRST_VERTEX)
|<br>
+ (BITFIELD64_BIT(SYSTEM_VALUE_F<wbr>IRST_VERTEX)
|<br>
BITFIELD64_BIT(SYSTEM_VALUE_BA<wbr>SE_INSTANCE)
|<br>
BITFIELD64_BIT(SYSTEM_VALUE_VE<wbr>RTEX_ID_ZERO_BASE)
|<br>
BITFIELD64_BIT(SYSTEM_VALUE_IN<wbr>STANCE_ID));<br>
@@ -279,7 +278,6 @@
brw_nir_lower_vs_inputs(nir_sh<wbr>ader
*nir,<br>
<br>
nir_intrinsic_set_base(load, num_inputs);<br>
switch
(intrin->intrinsic) {<br>
- case
nir_intrinsic_load_base_vertex<wbr>:<br>
case
nir_intrinsic_load_first_verte<wbr>x:<br>
nir_intrinsic_set_component(l<wbr>oad,
0);<br>
break;<br>
@@ -293,11 +291,15 @@
brw_nir_lower_vs_inputs(nir_sh<wbr>ader
*nir,<br>
nir_intrinsic_set_component(l<wbr>oad,
3);<br>
break;<br>
case
nir_intrinsic_load_draw_id:<br>
- /* gl_DrawID is stored
right after gl_VertexID and friends<br>
- * if any of them
exist.<br>
+ case
nir_intrinsic_load_base_vertex<wbr>:<br>
+ /* gl_DrawID and
gl_BaseVertex are stored right after<br>
+ gl_VertexID and
friends if any of them exist.<br>
*/<br>
nir_intrinsic_set_base(load, num_inputs +
has_sgvs);<br>
-
nir_intrinsic_set_component(lo<wbr>ad, 0);<br>
+ if
(intrin->intrinsic ==
nir_intrinsic_load_draw_id)<br>
+
nir_intrinsic_set_component(l<wbr>oad,
0);<br>
+ else<br>
+
nir_intrinsic_set_component(l<wbr>oad,
1);<br>
break;<br>
default:<br>
unreachable("Invalid
system value intrinsic");<br>
diff --git a/src/intel/compiler/brw_vec4.<wbr>cpp
b/src/intel/compiler/brw_vec4.<wbr>cpp<br>
index 1e384f5bf4d..d33caefdea9 100644<br>
--- a/src/intel/compiler/brw_vec4.<wbr>cpp<br>
+++ b/src/intel/compiler/brw_vec4.<wbr>cpp<br>
@@ -2825,14 +2825,19 @@
brw_compile_vs(const struct brw_compiler
*compiler, void *log_data,<br>
* incoming vertex attribute. So, add
an extra slot.<br>
*/<br>
if (shader->info.system_values_re<wbr>ad
&<br>
- (BITFIELD64_BIT(SYSTEM_VALUE_<wbr>BASE_VERTEX)
|<br>
- BITFIELD64_BIT(SYSTEM_VALUE_FI<wbr>RST_VERTEX)
|<br>
+ (BITFIELD64_BIT(SYSTEM_VALUE_<wbr>FIRST_VERTEX)
|<br>
BITFIELD64_BIT(SYSTEM_VALUE_B<wbr>ASE_INSTANCE)
|<br>
BITFIELD64_BIT(SYSTEM_VALUE_V<wbr>ERTEX_ID_ZERO_BASE)
|<br>
BITFIELD64_BIT(SYSTEM_VALUE_I<wbr>NSTANCE_ID)))
{<br>
nr_attribute_slots++;<br>
}<br>
<br>
+ if (shader->info.system_values_re<wbr>ad
&<br>
+ (BITFIELD64_BIT(SYSTEM_VALUE_<wbr>BASE_VERTEX)
|<br>
+ BITFIELD64_BIT(SYSTEM_VALUE_DR<wbr>AW_ID)))
{<br>
+ nr_attribute_slots++;<br>
+ }<br>
+<br>
if (shader->info.system_values_re<wbr>ad
&<br>
BITFIELD64_BIT(SYSTEM_VALUE_BA<wbr>SE_VERTEX))<br>
prog_data->uses_basevertex =
true;<br>
@@ -2853,12 +2858,9 @@
brw_compile_vs(const struct brw_compiler
*compiler, void *log_data,<br>
BITFIELD64_BIT(SYSTEM_VALUE_IN<wbr>STANCE_ID))<br>
prog_data->uses_instanceid =
true;<br>
<br>
- /* gl_DrawID has its very own vec4 */<br>
if (shader->info.system_values_re<wbr>ad
&<br>
- BITFIELD64_BIT(SYSTEM_VALUE_D<wbr>RAW_ID))
{<br>
+ BITFIELD64_BIT(SYSTEM_VALUE_D<wbr>RAW_ID))<br>
prog_data->uses_drawid = true;<br>
- nr_attribute_slots++;<br>
- }<br>
<br>
/* The 3DSTATE_VS documentation lists
the lower bound on "Vertex URB Entry<br>
* Read Length" as 1 in vec4 mode, and
0 in SIMD8 mode. Empirically, in<br>
diff --git a/src/mesa/drivers/dri/i965/br<wbr>w_context.h
b/src/mesa/drivers/dri/i965/br<wbr>w_context.h<br>
index c65a22c38bb..6758b34f47e 100644<br>
--- a/src/mesa/drivers/dri/i965/br<wbr>w_context.h<br>
+++ b/src/mesa/drivers/dri/i965/br<wbr>w_context.h<br>
@@ -898,20 +898,36 @@ struct brw_context<br>
} params;<br>
<br>
/**<br>
- * Buffer and offset used for
GL_ARB_shader_draw_parameters<br>
- * (for now, only gl_BaseVertex).<br>
+ * Buffer and offset used for
GL_ARB_shader_draw_parameters which will<br>
+ * point to the indirect buffer for
indirect draw calls.<br>
*/<br>
struct brw_bo *draw_params_bo;<br>
uint32_t draw_params_offset;<br>
<br>
+ struct {<br>
+ /**<br>
+ * The value of gl_DrawID for
the current _mesa_prim. This always comes<br>
+ * in from it's own vertex
buffer since it's not part of the indirect<br>
+ * draw parameters.<br>
+ */<br>
+ int gl_drawid;<br>
+<br>
+ /**<br>
+ * The value of gl_BaseVertex
for the current _mesa_prim. Although<br>
+ * gl_BaseVertex is part of the
indirect buffer for indexed draw calls,<br>
+ * that is not longer the case
for non-indexed draw calls, where it must<br>
+ * be zero, so we store it in a
different buffer.<br>
+ */<br>
+ int gl_basevertex;<br>
+ } derived_params;<br>
+<br>
/**<br>
- * The value of gl_DrawID for the
current _mesa_prim. This always comes<br>
- * in from it's own vertex buffer
since it's not part of the indirect<br>
- * draw parameters.<br>
+ * Buffer and offset used for
GL_ARB_shader_draw_parameters which
contains<br>
+ * parameters that are not present
in the indirect buffer. They will go in<br>
+ * their own vertex element.<br>
*/<br>
- int gl_drawid;<br>
- struct brw_bo *draw_id_bo;<br>
- uint32_t draw_id_offset;<br>
+ struct brw_bo
*derived_draw_params_bo;<br>
+ uint32_t
derived_draw_params_offset;<br>
<br>
/**<br>
* Pointer to the the buffer
storing the indirect draw parameters. It<br>
diff --git a/src/mesa/drivers/dri/i965/br<wbr>w_draw.c
b/src/mesa/drivers/dri/i965/br<wbr>w_draw.c<br>
index f51f083178e..e9ec8d585d2 100644<br>
--- a/src/mesa/drivers/dri/i965/br<wbr>w_draw.c<br>
+++ b/src/mesa/drivers/dri/i965/br<wbr>w_draw.c<br>
@@ -241,6 +241,14 @@ brw_emit_prim(struct
brw_context *brw,<br>
prim->indirect_offset + 12);<br>
brw_load_register_mem(brw,
GEN7_3DPRIM_START_INSTANCE, bo,<br>
prim->indirect_offset + 16);<br>
+<br>
+ /* Store the gl_BaseVertex value
in its vertex buffer */<br>
+ if
(brw->draw.derived_draw_params<wbr>_bo
!= NULL) {<br>
+ brw_store_register_mem32(brw,
brw->draw.derived_draw_params_<wbr>bo,<br>
+
GEN7_3DPRIM_BASE_VERTEX,<br>
+
brw->draw.derived_draw_<wbr>params_offset
+ 4);<br>
+ brw_emit_mi_flush(brw);<br>
+ }<br>
</blockquote>
<div><br>
</div>
<div>Oh, boy, this is tricky... First of
all, it's a bit of a bummer that we can't
just load the indirect buffer again for
this. Not too much to do about it, I
guess.<br>
<br>
</div>
<div>Second, there be very scary dragons
here. It turns out that, at least on
Haswell (and possibly other platforms),
reading from state registers while
rendering is in-flight can lead to GPU
hangs. Yes, I said "reading". We found
this out the hard way while working on
Vulkan indirect clear colors. The better
thing to do here would be to use GPRs when
available (I think they're safe but I'm
not sure) or to do a MI_COPY_MEM_MEM
which, of course, is only available on
gen8+. On Ivy Bridge (and haswell if
we're going to do a store_register_mem
from a state register), we need to do a
mi_flush *before* the store as well.<br>
</div>
<div> </div>
</div>
</div>
</div>
</blockquote>
<br>
</div>
</div>
I see that this is complicated, I have thought in a
different way to implement this.<br>
Instead of moving gl_BaseVertex to a VE2 and reading its
value from state registers:<br>
<br>
- VE1 remains as: <firstvertex, BaseInstance,
VertexID, InstanceID><br>
-> Patches 1-5 are still valid (I think) and we can
still calculate the VertexID as FirstVertex +
VertexIDZeroBased.<br>
<br>
- VE2 contains: <Draw ID, IsIndexedDraw, 0, 0>,<br>
->when asked for glBaseVertex
(nir_instrinsic_load_base_<wbr>vertex), we would return
the value stored in FirstVertex is the draw call is
indexed, zero if it is not.<br>
<br>
How does it sound?.<br>
</div>
</blockquote>
<div><br>
</div>
<div>That sounds fine to me. It's one extra instruciton in
the shader (it could be an AND if IsIndexedDraw is 0/~0)
and lets us avoid trying to do command-stream copying of
data. If I understand correcctly, Vulkan will never hit
this path because it will always use FIRST_VERETX and not
BASE_VERTEX. Is that correct?<br>
</div>
</div>
</div>
</div>
</blockquote>
<br>
Yes, it won't be hit by Vulkan.<br>
<br>
<blockquote type="cite"
cite="mid:CAOFGe97jddBanqjPA-C7K3csebV2G1-FnuAb0tu5Q_o1DyiNvw@mail.gmail.com">
<div dir="ltr">
<div class="gmail_extra">
<div class="gmail_quote">
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">
<div text="#000000" bgcolor="#FFFFFF">
<div>
<div class="h5">
<blockquote type="cite">
<div dir="ltr">
<div class="gmail_extra">
<div class="gmail_quote">
<blockquote class="gmail_quote"
style="margin:0 0 0 .8ex;border-left:1px
#ccc solid;padding-left:1ex"> }
else {<br>
brw_load_register_mem(brw,
GEN7_3DPRIM_START_INSTANCE, bo,<br>
prim->indirect_offset + 12);<br>
@@ -815,7 +823,7 @@
brw_draw_single_prim(struct gl_context
*ctx,<br>
}<br>
<br>
/* Determine if we need to flag
BRW_NEW_VERTICES for updating the<br>
- * gl_BaseVertexARB or
gl_BaseInstanceARB values. For indirect
draw, we<br>
+ * firstvertex or gl_BaseInstanceARB
values. For indirect draw, we<br>
* always flag if the shader uses one
of the values. For direct draws,<br>
* we only flag if the values change.<br>
*/<br>
@@ -825,16 +833,12 @@
brw_draw_single_prim(struct gl_context
*ctx,<br>
const struct brw_vs_prog_data
*vs_prog_data =<br>
brw_vs_prog_data(brw->vs.<wbr>base.prog_data);<br>
if (prim_id > 0) {<br>
- const bool uses_firstvertex =<br>
- vs_prog_data->uses_basevertex
||<br>
- vs_prog_data->uses_firstverte<wbr>x;<br>
-<br>
const bool uses_draw_parameters =<br>
- uses_firstvertex ||<br>
+ vs_prog_data->uses_<wbr>firstvertex
||<br>
vs_prog_data->uses_baseinstanc<wbr>e;<br>
<br>
if ((uses_draw_parameters
&& prim->is_indirect) ||<br>
- (uses_firstvertex &&<br>
+
(vs_prog_data->uses_firstverte<wbr>x
&&<br>
brw->draw.params.firstvertex !=
new_firstvertex) ||<br>
(vs_prog_data->uses_baseinsta<wbr>nce
&&<br>
brw->draw.params.gl_baseinstan<wbr>ce
!= new_baseinstance))<br>
@@ -861,17 +865,28 @@
brw_draw_single_prim(struct gl_context
*ctx,<br>
}<br>
<br>
/* gl_DrawID always needs its own
vertex buffer since it's not part of<br>
- * the indirect parameter buffer. If
the program uses gl_DrawID we need<br>
- * to flag BRW_NEW_VERTICES. For the
first iteration, we don't have<br>
- * valid vs_prog_data, but we always
flag BRW_NEW_VERTICES before<br>
- * the loop.<br>
+ * the indirect parameter buffer. This
is the same for gl_BaseVertex, which<br>
+ * is not part of the indirect
parameter buffer for non-indexed draw
calls.<br>
+ * If the program uses gl_DrawID or,
uses gl_BaseVertex and it is an indirect<br>
+ * draw call or the value has changed,
we need to flag BRW_NEW_VERTICES.<br>
+ * For the first iteration, we don't
have valid vs_prog_data, but we always<br>
+ * flag BRW_NEW_VERTICES before the
loop.<br>
*/<br>
- brw->draw.gl_drawid =
prim->draw_id;<br>
- brw_bo_unreference(brw->draw.<wbr>draw_id_bo);<br>
- brw->draw.draw_id_bo = NULL;<br>
- if (prim_id > 0 &&
vs_prog_data->uses_drawid)<br>
+ const int new_basevertex =
prim->indexed ? prim->basevertex :
0;<br>
+ if (prim_id > 0 &&<br>
+ (vs_prog_data->uses_drawid ||<br>
+ (vs_prog_data->uses_basevertex
&&<br>
+ (prim->is_indirect ||<br>
+
brw->draw.derived_params.gl_ba<wbr>severtex
!= new_basevertex))))<br>
brw->ctx.NewDriverState |=
BRW_NEW_VERTICES;<br>
<br>
+ brw->draw.derived_params.gl_d<wbr>rawid
= prim->draw_id;<br>
+ brw->draw.derived_params.gl_b<wbr>asevertex
= new_basevertex;<br>
+<br>
+ brw_bo_unreference(brw->draw.<wbr>derived_draw_params_bo);<br>
+ brw->draw.derived_draw_<wbr>params_bo
= NULL;<br>
+ brw->draw.derived_draw_<wbr>params_offset
= 0;<br>
+<br>
if (devinfo->gen < 6)<br>
brw_set_prim(brw, prim);<br>
else<br>
diff --git a/src/mesa/drivers/dri/i965/br<wbr>w_draw_upload.c
b/src/mesa/drivers/dri/i965/br<wbr>w_draw_upload.c<br>
index 7573f780f23..54ba951d6fd 100644<br>
--- a/src/mesa/drivers/dri/i965/br<wbr>w_draw_upload.c<br>
+++ b/src/mesa/drivers/dri/i965/br<wbr>w_draw_upload.c<br>
@@ -704,11 +704,11 @@
brw_prepare_shader_draw_parame<wbr>ters(struct
brw_context *brw)<br>
const struct brw_vs_prog_data
*vs_prog_data =<br>
brw_vs_prog_data(brw->vs.<wbr>base.prog_data);<br>
<br>
- const bool uses_firstvertex =<br>
- vs_prog_data->uses_basevertex ||
vs_prog_data->uses_firstvertex<wbr>;<br>
+ const bool uses_derived_draw_params =<br>
+ vs_prog_data->uses_basevertex ||
vs_prog_data->uses_drawid;<br>
<br>
/* For non-indirect draws, upload the
shader draw parameters */<br>
- if ((uses_firstvertex ||
vs_prog_data->uses_baseinstanc<wbr>e)
&&<br>
+ if ((vs_prog_data->uses_firstvert<wbr>ex
|| vs_prog_data->uses_baseinstanc<wbr>e)
&&<br>
brw->draw.draw_params_bo ==
NULL) {<br>
brw_upload_data(&brw->upload,<br>
&brw->draw.params,
sizeof(brw->draw.params), 4,<br>
@@ -716,11 +716,11 @@
brw_prepare_shader_draw_parame<wbr>ters(struct
brw_context *brw)<br>
&brw->draw.draw_params_<wbr>offset);<br>
}<br>
<br>
- if (vs_prog_data->uses_drawid) {<br>
+ if (uses_derived_draw_params) {<br>
brw_upload_data(&brw->upload,<br>
-
&brw->draw.gl_drawid,
sizeof(brw->draw.gl_drawid), 4,<br>
-
&brw->draw.draw_id_bo,<br>
-
&brw->draw.draw_id_offset);<br>
+
&brw->draw.derived_params,
sizeof(brw->draw.derived_param<wbr>s),
4,<br>
+
&brw->draw.derived_draw_params<wbr>_bo,<br>
+
&brw->draw.derived_draw_params<wbr>_offset);<br>
}<br>
}<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/ge<wbr>nX_state_upload.c
b/src/mesa/drivers/dri/i965/ge<wbr>nX_state_upload.c<br>
index 1a32c60ae34..8323446b4ac 100644<br>
--- a/src/mesa/drivers/dri/i965/ge<wbr>nX_state_upload.c<br>
+++ b/src/mesa/drivers/dri/i965/ge<wbr>nX_state_upload.c<br>
@@ -539,16 +539,14 @@
genX(emit_vertices)(struct brw_context
*brw)<br>
}<br>
#endif<br>
<br>
- const bool uses_firstvertex =<br>
- vs_prog_data->uses_basevertex ||
vs_prog_data->uses_firstvertex<wbr>;<br>
-<br>
- const bool needs_sgvs_element =
(uses_firstvertex ||<br>
+ const bool needs_sgvs_element =
(vs_prog_data->uses_firstverte<wbr>x ||<br>
vs_prog_data->uses_baseinstan<wbr>ce
||<br>
vs_prog_data->uses_instanceid ||<br>
vs_prog_data->uses_vertexid);<br>
<br>
unsigned nr_elements =<br>
- brw->vb.nr_enabled +
needs_sgvs_element +
vs_prog_data->uses_drawid;<br>
+ brw->vb.nr_enabled +
needs_sgvs_element +<br>
+ (vs_prog_data->uses_drawid ||
vs_prog_data->uses_basevertex)<wbr>;<br>
<br>
#if GEN_GEN < 8<br>
/* If any of the formats of vb.enabled
needs more that one upload, we need<br>
@@ -589,10 +587,15 @@
genX(emit_vertices)(struct brw_context
*brw)<br>
<br>
/* Now emit 3DSTATE_VERTEX_BUFFERS and
3DSTATE_VERTEX_ELEMENTS packets. */<br>
const bool uses_draw_params =<br>
- uses_firstvertex ||<br>
+ vs_prog_data->uses_firstvertex
||<br>
vs_prog_data->uses_baseinstan<wbr>ce;<br>
+<br>
+ const bool uses_derived_draw_params =<br>
+ vs_prog_data->uses_drawid ||<br>
+ vs_prog_data->uses_basevertex;<br>
+<br>
const unsigned nr_buffers =
brw->vb.nr_buffers +<br>
- uses_draw_params +
vs_prog_data->uses_drawid;<br>
+ uses_draw_params +
uses_derived_draw_params;<br>
<br>
if (nr_buffers) {<br>
assert(nr_buffers <= (GEN_GEN
>= 6 ? 33 : 17));<br>
@@ -626,11 +629,11 @@
genX(emit_vertices)(struct brw_context
*brw)<br>
0 /* step rate */);<br>
}<br>
<br>
- if (vs_prog_data->uses_drawid) {<br>
+ if (uses_derived_draw_params) {<br>
dw =
genX(emit_vertex_buffer_state)<wbr>(brw,
dw, brw->vb.nr_buffers + 1,<br>
-
brw->draw.draw_id_bo,<br>
-
brw->draw.draw_id_offset,<br>
-
brw->draw.draw_id_bo->size,<br>
+
brw->draw.derived_draw_<wbr>params_bo,<br>
+
brw->draw.derived_draw_<wbr>params_offset,<br>
+
brw->draw.derived_draw_<wbr>params_bo->size,<br>
0 /* stride */,<br>
0 /* step rate */);<br>
}<br>
@@ -772,7 +775,7 @@
genX(emit_vertices)(struct brw_context
*brw)<br>
};<br>
<br>
#if GEN_GEN >= 8<br>
- if (uses_firstvertex ||<br>
+ if
(vs_prog_data->uses_firstverte<wbr>x ||<br>
vs_prog_data->uses_baseinstan<wbr>ce)
{<br>
elem_state.VertexBufferIndex =
brw->vb.nr_buffers;<br>
elem_state.SourceElementFormat =
ISL_FORMAT_R32G32_UINT;<br>
@@ -782,11 +785,10 @@
genX(emit_vertices)(struct brw_context
*brw)<br>
#else<br>
elem_state.VertexBufferIndex =
brw->vb.nr_buffers;<br>
elem_state.<wbr>SourceElementFormat
= ISL_FORMAT_R32G32_UINT;<br>
- if (uses_firstvertex)<br>
+ if
(vs_prog_data->uses_firstverte<wbr>x ||
vs_prog_data->uses_baseinstanc<wbr>e) {<br>
elem_state.Component0Control =
VFCOMP_STORE_SRC;<br>
-<br>
- if
(vs_prog_data->uses_baseinstan<wbr>ce)<br>
elem_state.Component1Control =
VFCOMP_STORE_SRC;<br>
+ }<br>
<br>
if (vs_prog_data->uses_vertexid)<br>
elem_state.Component2Control =
VFCOMP_STORE_VID;<br>
@@ -799,13 +801,13 @@
genX(emit_vertices)(struct brw_context
*brw)<br>
dw +=
GENX(VERTEX_ELEMENT_STATE_leng<wbr>th);<br>
}<br>
<br>
- if (vs_prog_data->uses_drawid) {<br>
+ if (vs_prog_data->uses_drawid ||
vs_prog_data->uses_basevertex) {<br>
struct GENX(VERTEX_ELEMENT_STATE)
elem_state = {<br>
.Valid = true,<br>
.VertexBufferIndex =
brw->vb.nr_buffers + 1,<br>
- .SourceElementFormat =
ISL_FORMAT_R32_UINT,<br>
+ .SourceElementFormat =
ISL_FORMAT_R32G32_UINT,<br>
.Component0Control =
VFCOMP_STORE_SRC,<br>
- .Component1Control =
VFCOMP_STORE_0,<br>
+ .Component1Control =
VFCOMP_STORE_SRC,<br>
.Component2Control =
VFCOMP_STORE_0,<br>
.Component3Control =
VFCOMP_STORE_0,<br>
#if GEN_GEN < 5<br>
<span class="m_641628760359447415HOEnZb"><font
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