<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Wed, Apr 18, 2018 at 5:54 AM, Nicolai Hähnle <span dir="ltr"><<a href="mailto:nhaehnle@gmail.com" target="_blank">nhaehnle@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="m_5702272431126212817HOEnZb"><div class="m_5702272431126212817h5">On 17.04.2018 02:41, Marek Olšák wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
From: Marek Olšák <<a href="mailto:marek.olsak@amd.com" target="_blank">marek.olsak@amd.com</a>><br>
<br>
---<br>
src/amd/common/ac_surface.c | 14 +++++++++++++-<br>
1 file changed, 13 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c<br>
index 7558dd91e34..c209b209da2 100644<br>
--- a/src/amd/common/ac_surface.c<br>
+++ b/src/amd/common/ac_surface.c<br>
@@ -344,24 +344,36 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,<br>
AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;<br>
AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;<br>
AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeInde<wbr>x;<br>
ret = AddrComputeDccInfo(addrlib,<br>
AddrDccIn,<br>
AddrDccOut);<br>
if (ret == ADDR_OK) {<br>
surf_level->dcc_offset = surf->dcc_size;<br>
- surf_level->dcc_fast_clear_si<wbr>ze = AddrDccOut->dccFastClearSize;<br>
surf->num_dcc_levels = level + 1;<br>
surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;<br>
surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);<br>
+<br>
+ /* If the DCC size of a subresource (1 mip level or 1 slice)<br>
+ * is not aligned, the DCC memory layout is not contiguous for<br>
+ * that subresource, which means we can't use fast clear.<br>
+ *<br>
+ * We only do fast clears for whole mipmap levels. If we did<br>
+ * per-slice fast clears, the same restriction would apply.<br>
+ * (i.e. only compute the slice size and see if it's aligned)<br>
+ */<br>
+ if (level == config->info.levels - 1 || AddrDccOut->dccRamSizeAligned)<br>
</blockquote>
<br></div></div>
Are you sure that the last level is always okay? It seems possible that the last and second-to-last level end up interleaved due to swizzling.<br>
<br>
The catch is that you'd probably only ever notice this with a truncated mip-tree.<br></blockquote><div><br></div><div>This condition was copied from amdvlk. I guess that if the second-to-last level is unaligned, the last level would also be unaligned.<br><br></div><div>We never use fast clear for non-zero level. For now, we only have to make sure that level 0 is contiguous.<br><br></div><div>Marek<br></div></div><br></div></div>