<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Wed, Apr 11, 2018 at 12:20 AM, Iago Toral Quiroga <span dir="ltr"><<a href="mailto:itoral@igalia.com" target="_blank">itoral@igalia.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">The lowering pass was specialized to act on 64-bit to 32-bit conversions only,<br>
but the implementation is valid for other cases.<br>
---<br>
src/intel/compiler/brw_fs_<wbr>lower_conversions.cpp | 5 ++++-<br>
src/intel/compiler/brw_fs_nir.<wbr>cpp | 14 +++-----------<br>
2 files changed, 7 insertions(+), 12 deletions(-)<br>
<br>
diff --git a/src/intel/compiler/brw_fs_<wbr>lower_conversions.cpp b/src/intel/compiler/brw_fs_<wbr>lower_conversions.cpp<br>
index 663c9674c49..f95b39d3e86 100644<br>
--- a/src/intel/compiler/brw_fs_<wbr>lower_conversions.cpp<br>
+++ b/src/intel/compiler/brw_fs_<wbr>lower_conversions.cpp<br>
@@ -54,7 +54,7 @@ fs_visitor::lower_conversions(<wbr>)<br>
bool saturate = inst->saturate;<br>
<br>
if (supports_type_conversion(<wbr>inst)) {<br>
- if (get_exec_type_size(inst) == 8 && type_sz(inst->dst.type) < 8) {<br>
+ if (type_sz(inst->dst.type) < get_exec_type_size(inst)) {<br>
/* From the Broadwell PRM, 3D Media GPGPU, "Double Precision Float to<br>
* Single Precision Float":<br>
*<br>
@@ -64,6 +64,9 @@ fs_visitor::lower_conversions(<wbr>)<br>
* So we need to allocate a temporary that's two registers, and then do<br>
* a strided MOV to get the lower DWord of every Qword that has the<br>
* result.<br>
+ *<br>
+ * This restriction applies, in general, whenever we convert to<br>
+ * a type with a smaller bit-size.<br>
*/<br>
fs_reg temp = ibld.vgrf(get_exec_type(inst))<wbr>;<br>
fs_reg strided_temp = subscript(temp, dst.type, 0);<br>
diff --git a/src/intel/compiler/brw_fs_<wbr>nir.cpp b/src/intel/compiler/brw_fs_<wbr>nir.cpp<br>
index f40a3540e31..5e0dd37eefd 100644<br>
--- a/src/intel/compiler/brw_fs_<wbr>nir.cpp<br>
+++ b/src/intel/compiler/brw_fs_<wbr>nir.cpp<br>
@@ -753,19 +753,9 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)<br>
*/<br>
<br>
case nir_op_f2f16_undef:<br>
- case nir_op_i2i16:<br>
- case nir_op_u2u16: {<br>
- /* TODO: Fixing aligment rules for conversions from 32-bits to<br>
- * 16-bit types should be moved to lower_conversions<br>
- */<br>
- fs_reg tmp = bld.vgrf(op[0].type, 1);<br>
- tmp = subscript(tmp, result.type, 0);<br>
- inst = bld.MOV(tmp, op[0]);<br>
- inst->saturate = instr->dest.saturate;<br>
- inst = bld.MOV(result, tmp);<br>
+ inst = bld.MOV(result, op[0]);<br>
inst->saturate = instr->dest.saturate;<br>
break;<br></blockquote><div><br></div><div>It appears to me that we can move f2f16_undef to the block below as well. Without or without that,<br><br></div><div>Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
- }<br>
<br>
case nir_op_f2f64:<br>
case nir_op_f2i64:<br>
@@ -803,6 +793,8 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)<br>
case nir_op_f2u32:<br>
case nir_op_i2i32:<br>
case nir_op_u2u32:<br>
+ case nir_op_i2i16:<br>
+ case nir_op_u2u16:<br>
inst = bld.MOV(result, op[0]);<br>
inst->saturate = instr->dest.saturate;<br>
break;<br>
<span class="HOEnZb"><font color="#888888">-- <br>
2.14.1<br>
<br>
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