<div dir="ltr">Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Apr 11, 2018 at 12:20 AM, Iago Toral Quiroga <span dir="ltr"><<a href="mailto:itoral@igalia.com" target="_blank">itoral@igalia.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">We need to use 16-bit constants with 16-bit instructions,<br>
otherwise we get the following validation error:<br>
<br>
"Destination stride must be equal to the ratio of the sizes of<br>
 the execution data type to the destination type"<br>
<br>
Because the execution data type is 4B due to the 32-bit integer<br>
constant.<br>
---<br>
 src/intel/compiler/brw_fs_nir.<wbr>cpp | 17 ++++++++++++-----<br>
 1 file changed, 12 insertions(+), 5 deletions(-)<br>
<br>
diff --git a/src/intel/compiler/brw_fs_<wbr>nir.cpp b/src/intel/compiler/brw_fs_<wbr>nir.cpp<br>
index 6c4bcd1c113..f40a3540e31 100644<br>
--- a/src/intel/compiler/brw_fs_<wbr>nir.cpp<br>
+++ b/src/intel/compiler/brw_fs_<wbr>nir.cpp<br>
@@ -863,17 +863,24 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)<br>
       break;<br>
    }<br>
<br>
-   case nir_op_isign:<br>
+   case nir_op_isign: {<br>
       /*  ASR(val, 31) -> negative val generates 0xffffffff (signed -1).<br>
        *               -> non-negative val generates 0x00000000.<br>
        *  Predicated OR sets 1 if val is positive.<br>
        */<br>
-      assert(nir_dest_bit_size(<wbr>instr->dest.dest) < 64);<br>
-      bld.CMP(bld.null_reg_d(), op[0], brw_imm_d(0), BRW_CONDITIONAL_G);<br>
-      bld.ASR(result, op[0], brw_imm_d(31));<br>
-      inst = bld.OR(result, result, brw_imm_d(1));<br>
+      uint32_t bit_size = nir_dest_bit_size(instr->dest.<wbr>dest);<br>
+      assert(bit_size == 32 || bit_size == 16);<br>
+<br>
+      fs_reg zero = bit_size == 32 ? brw_imm_d(0) : brw_imm_w(0);<br>
+      fs_reg one = bit_size == 32 ? brw_imm_d(1) : brw_imm_w(1);<br>
+      fs_reg shift = bit_size == 32 ? brw_imm_d(31) : brw_imm_w(15);<br>
+<br>
+      bld.CMP(bld.null_reg_d(), op[0], zero, BRW_CONDITIONAL_G);<br>
+      bld.ASR(result, op[0], shift);<br>
+      inst = bld.OR(result, result, one);<br>
       inst->predicate = BRW_PREDICATE_NORMAL;<br>
       break;<br>
+   }<br>
<br>
    case nir_op_frcp:<br>
       inst = bld.emit(SHADER_OPCODE_RCP, result, op[0]);<br>
<span class="HOEnZb"><font color="#888888">-- <br>
2.14.1<br>
<br>
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</font></span></blockquote></div><br></div>