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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - radv: VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT and bringing down initial pipeline compile times"
href="https://bugs.freedesktop.org/show_bug.cgi?id=106246#c3">Comment # 3</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - radv: VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT and bringing down initial pipeline compile times"
href="https://bugs.freedesktop.org/show_bug.cgi?id=106246">bug 106246</a>
from <span class="vcard"><a class="email" href="mailto:nhaehnle@gmail.com" title="Nicolai Hähnle <nhaehnle@gmail.com>"> <span class="fn">Nicolai Hähnle</span></a>
</span></b>
<pre>As long as scratch buffer support is robust, removing LLVM IR optimization
passes is probably not a problem, though you really do want mem2reg and I don't
think we spend much time in the others (at least radeonsi didn't, last time I
checked).
Using the -O0 settings for the codegen backend is a lot riskier. Our compute
folks have done some work fixing bugs there, but I really wouldn't recommend
it.</pre>
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