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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - radv: VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT and bringing down initial pipeline compile times"
href="https://bugs.freedesktop.org/show_bug.cgi?id=106246#c8">Comment # 8</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - radv: VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT and bringing down initial pipeline compile times"
href="https://bugs.freedesktop.org/show_bug.cgi?id=106246">bug 106246</a>
from <span class="vcard"><a class="email" href="mailto:nhaehnle@gmail.com" title="Nicolai Hähnle <nhaehnle@gmail.com>"> <span class="fn">Nicolai Hähnle</span></a>
</span></b>
<pre>The fast register allocator stresses the spill logic a lot. I believe it
basically spills at the end of every basic block and reloads at the start of
every basic block. Plus it's not very well tested with AMDGPU, so this really
isn't surprising.</pre>
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