<div dir="ltr"><div>Would this work for you instead?</div><div><a href="https://cgit.freedesktop.org/~mareko/mesa/commit/?h=user-stride&id=1fadff480e53fb691add602933c5d711d7e4b6e0">https://cgit.freedesktop.org/~mareko/mesa/commit/?h=user-stride&id=1fadff480e53fb691add602933c5d711d7e4b6e0</a></div><div><br></div><div>Marek<br></div><div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, May 14, 2018 at 5:10 PM, Bas Nieuwenhuizen <span dir="ltr"><<a href="mailto:bas@basnieuwenhuizen.nl" target="_blank">bas@basnieuwenhuizen.nl</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">There are non-shared linear images too, and those don't<br>
need the extra alignment at all.<br>
<br>
So just keep track of whether the image can be exported.<br>
<br>
Fixes: e361970ed73 "radv: Add support for IMG_DATA_FORMAT_32_32_32."<br>
---<br>
src/amd/common/ac_surface.c | 10 ++++++----<br>
1 file changed, 6 insertions(+), 4 deletions(-)<br>
<br>
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c<br>
index 9e742dc8a45..f6c4cd7db0f 100644<br>
--- a/src/amd/common/ac_surface.c<br>
+++ b/src/amd/common/ac_surface.c<br>
@@ -281,7 +281,7 @@ static int surf_config_sanity(const struct ac_surf_config *config,<br>
static int gfx6_compute_level(ADDR_HANDLE addrlib,<br>
const struct ac_surf_config *config,<br>
struct radeon_surf *surf, bool is_stencil,<br>
- unsigned level, bool compressed,<br>
+ unsigned level, bool compressed, bool shareable,<br>
ADDR_COMPUTE_SURFACE_INFO_<wbr>INPUT *AddrSurfInfoIn,<br>
ADDR_COMPUTE_SURFACE_INFO_<wbr>OUTPUT *AddrSurfInfoOut,<br>
ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,<br>
@@ -301,7 +301,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,<br>
*/<br>
if (config->info.levels == 1 &&<br>
AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&<br>
- AddrSurfInfoIn->bpp) {<br>
+ AddrSurfInfoIn->bpp && shareable) {<br>
unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);<br>
<br>
assert(util_is_power_of_two_<wbr>or_zero(AddrSurfInfoIn->bpp));<br>
@@ -560,6 +560,7 @@ static int gfx6_compute_surface(ADDR_<wbr>HANDLE addrlib,<br>
{<br>
unsigned level;<br>
bool compressed;<br>
+ bool shareable;<br>
ADDR_COMPUTE_SURFACE_INFO_<wbr>INPUT AddrSurfInfoIn = {0};<br>
ADDR_COMPUTE_SURFACE_INFO_<wbr>OUTPUT AddrSurfInfoOut = {0};<br>
ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};<br>
@@ -579,6 +580,7 @@ static int gfx6_compute_surface(ADDR_<wbr>HANDLE addrlib,<br>
AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;<br>
<br>
compressed = surf->blk_w == 4 && surf->blk_h == 4;<br>
+ shareable = (surf->flags & RADEON_SURF_SHAREABLE);<br>
<br>
/* MSAA requires 2D tiling. */<br>
if (config->info.samples > 1)<br>
@@ -773,7 +775,7 @@ static int gfx6_compute_surface(ADDR_<wbr>HANDLE addrlib,<br>
if (!only_stencil) {<br>
for (level = 0; level < config->info.levels; level++) {<br>
r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,<br>
- &AddrSurfInfoIn, &AddrSurfInfoOut,<br>
+ shareable, &AddrSurfInfoIn, &AddrSurfInfoOut,<br>
&AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);<br>
if (r)<br>
return r;<br>
@@ -820,7 +822,7 @@ static int gfx6_compute_surface(ADDR_<wbr>HANDLE addrlib,<br>
<br>
for (level = 0; level < config->info.levels; level++) {<br>
r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,<br>
- &AddrSurfInfoIn, &AddrSurfInfoOut,<br>
+ shareable, &AddrSurfInfoIn, &AddrSurfInfoOut,<br>
&AddrDccIn, &AddrDccOut,<br>
NULL, NULL);<br>
if (r)<br>
<span class="gmail-HOEnZb"><font color="#888888">-- <br>
2.17.0<br>
<br>
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</font></span></blockquote></div><br></div></div></div>