<div dir="ltr">ping<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, May 16, 2018 at 9:47 PM, Marek Olšák <span dir="ltr"><<a href="mailto:maraeo@gmail.com" target="_blank">maraeo@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Marek Olšák <<a href="mailto:marek.olsak@amd.com">marek.olsak@amd.com</a>><br>
<br>
---<br>
 src/amd/common/ac_surface.c | 13 +++++++++++--<br>
 1 file changed, 11 insertions(+), 2 deletions(-)<br>
<br>
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c<br>
index 9e742dc8a45..47de522d15d 100644<br>
--- a/src/amd/common/ac_surface.c<br>
+++ b/src/amd/common/ac_surface.c<br>
@@ -927,22 +927,31 @@ static int gfx6_compute_surface(ADDR_<wbr>HANDLE addrlib,<br>
                 *<br>
                 * "dcc_alignment * 4" was determined by trial and error.<br>
                 */<br>
                surf->dcc_size = align64(surf->surf_size >> 8,<br>
                                         surf->dcc_alignment * 4);<br>
        }<br>
<br>
        /* Make sure HTILE covers the whole miptree, because the shader reads<br>
         * TC-compatible HTILE even for levels where it's disabled by DB.<br>
         */<br>
-       if (surf->htile_size && config->info.levels > 1)<br>
-               surf->htile_size *= 2;<br>
+       if (surf->htile_size && config->info.levels > 1 &&<br>
+           surf->flags & RADEON_SURF_TC_COMPATIBLE_<wbr>HTILE) {<br>
+               /* MSAA can't occur with levels > 1, so ignore the sample count. */<br>
+               const unsigned total_pixels = surf->surf_size / surf->bpe;<br>
+               const unsigned htile_block_size = 8 * 8;<br>
+               const unsigned htile_element_size = 4;<br>
+<br>
+               surf->htile_size = (total_pixels / htile_block_size) *<br>
+                                  htile_element_size;<br>
+               surf->htile_size = align(surf->htile_size, surf->htile_alignment);<br>
+       }<br>
<br>
        surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_<wbr>ALIGNED;<br>
        surf->is_displayable = surf->is_linear ||<br>
                               surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||<br>
                               surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;<br>
        return 0;<br>
 }<br>
<br>
 /* This is only called when expecting a tiled layout. */<br>
 static int<br>
<span class="HOEnZb"><font color="#888888">-- <br>
2.17.0<br>
<br>
</font></span></blockquote></div><br></div>