<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Mon, May 28, 2018 at 3:52 AM, Nicolai Hähnle <span dir="ltr"><<a href="mailto:nhaehnle@gmail.com" target="_blank">nhaehnle@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Nicolai Hähnle <<a href="mailto:nicolai.haehnle@amd.com">nicolai.haehnle@amd.com</a>><br>
<br>
The only effect this has is that written cache lines are immediately<br>
freed in L1$. We're not going to read the data again, so it's better<br>
to leave room for other things in the cache.<br>
---<br>
src/gallium/drivers/radeonsi/<wbr>si_shader_tgsi_mem.c | 12 +++++++++++-<br>
1 file changed, 11 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/src/gallium/drivers/<wbr>radeonsi/si_shader_tgsi_mem.c b/src/gallium/drivers/<wbr>radeonsi/si_shader_tgsi_mem.c<br>
index f4140bb0e2d..c06d0c6edfa 100644<br>
--- a/src/gallium/drivers/<wbr>radeonsi/si_shader_tgsi_mem.c<br>
+++ b/src/gallium/drivers/<wbr>radeonsi/si_shader_tgsi_mem.c<br>
@@ -714,20 +714,26 @@ static void store_emit_buffer(<br>
offset = base_offset;<br>
if (start != 0) {<br>
offset = LLVMBuildAdd(<br>
builder, offset,<br>
LLVMConstInt(ctx->i32, start * 4, 0), "");<br>
}<br>
<br>
emit_data->args[0] = data;<br>
emit_data->args[3] = offset;<br>
<br>
+ if (writeonly_memory) {<br>
+ /* Set GLC for write-only memory, so that we don't<br>
+ * leave cache lines in L1$. */<br>
+ emit_data->args[3] = ctx->ac.i1true;<br>
+ }<br>
+<br>
lp_build_intrinsic(<br>
builder, intrinsic_name, emit_data->dst_type,<br>
emit_data->args, emit_data->arg_count,<br>
ac_get_store_intr_attribs(<wbr>writeonly_memory));<br>
}<br>
}<br>
<br>
static void store_emit_memory(<br>
struct si_shader_context *ctx,<br>
struct lp_build_emit_data *emit_data)<br>
@@ -793,24 +799,28 @@ static void store_emit(<br>
args.opcode = ac_image_store;<br>
args.data[0] = emit_data->args[0];<br>
args.resource = emit_data->args[1];<br>
memcpy(args.coords, &emit_data->args[2], sizeof(args.coords));<br>
args.dim = ac_image_dim_from_tgsi_target(<wbr>ctx->screen, inst->Memory.Texture);<br>
args.attributes = ac_get_store_intr_attribs(<wbr>writeonly_memory);<br>
args.dmask = 0xf;<br></blockquote><div><br></div><div>There is one more store above this block, but anyway:</div><div><br></div><div>Reviewed-by: Marek Olšák <<a href="mailto:marek.olsak@amd.com">marek.olsak@amd.com</a>></div><div><br></div><div>Marek<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
/* Workaround for 8bit/16bit TC L1 write corruption bug on SI.<br>
* All store opcodes not aligned to a dword are affected.<br>
+ *<br>
+ * Also set GLC for writeonly memory, so that we don't leave<br>
+ * cache lines in L1.<br>
*/<br>
bool force_glc = ctx->screen->info.chip_class == SI;<br>
if (force_glc ||<br>
- inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE))<br>
+ inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ||<br>
+ writeonly_memory)<br>
args.cache_policy = ac_glc;<br>
<br>
emit_data->output[emit_data-><wbr>chan] =<br>
ac_build_image_opcode(&ctx-><wbr>ac, &args);<br>
}<br>
}<br>
<br>
static void atomic_fetch_args(<br>
struct lp_build_tgsi_context * bld_base,<br>
struct lp_build_emit_data * emit_data)<br>
<span class="HOEnZb"><font color="#888888">-- <br>
2.14.1<br>
<br>
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