<div dir="ltr"><div>I pushed the series, thanks!</div><div><br></div><div>Marek<br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Jun 7, 2018 at 12:13 PM, Sonny Jiang <span dir="ltr"><<a href="mailto:sonny.jiang@amd.com" target="_blank">sonny.jiang@amd.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets<br>
<br>
Signed-off-by: Sonny Jiang <<a href="mailto:sonny.jiang@amd.com">sonny.jiang@amd.com</a>><br>
---<br>
src/gallium/drivers/radeonsi/<wbr>si_state.h | 3 ++<br>
src/gallium/drivers/radeonsi/<wbr>si_state_binning.c | 44 +++++++++++++------------<br>
2 files changed, 26 insertions(+), 21 deletions(-)<br>
<br>
diff --git a/src/gallium/drivers/<wbr>radeonsi/si_state.h b/src/gallium/drivers/<wbr>radeonsi/si_state.h<br>
index 941d154..8232e34 100644<br>
--- a/src/gallium/drivers/<wbr>radeonsi/si_state.h<br>
+++ b/src/gallium/drivers/<wbr>radeonsi/si_state.h<br>
@@ -232,6 +232,9 @@ enum si_tracked_reg {<br>
SI_TRACKED_PA_CL_VS_OUT_CNTL,<br>
SI_TRACKED_PA_CL_CLIP_CNTL,<br>
<br>
+ SI_TRACKED_PA_SC_BINNER_CNTL_<wbr>0,<br>
+ SI_TRACKED_DB_DFSM_CONTROL,<br>
+<br>
SI_NUM_TRACKED_REGS,<br>
};<br>
<br>
diff --git a/src/gallium/drivers/<wbr>radeonsi/si_state_binning.c b/src/gallium/drivers/<wbr>radeonsi/si_state_binning.c<br>
index 2605b59..665c11f 100644<br>
--- a/src/gallium/drivers/<wbr>radeonsi/si_state_binning.c<br>
+++ b/src/gallium/drivers/<wbr>radeonsi/si_state_binning.c<br>
@@ -325,13 +325,13 @@ static struct uvec2 si_get_depth_bin_size(struct si_context *sctx)<br>
<br>
static void si_emit_dpbb_disable(struct si_context *sctx)<br>
{<br>
- struct radeon_winsys_cs *cs = sctx->gfx_cs;<br>
-<br>
- radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,<br>
- S_028C44_BINNING_MODE(V_<wbr>028C44_DISABLE_BINNING_USE_<wbr>LEGACY_SC) |<br>
- S_028C44_DISABLE_START_OF_<wbr>PRIM(1));<br>
- radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,<br>
- S_028060_PUNCHOUT_MODE(V_<wbr>028060_FORCE_OFF));<br>
+ radeon_opt_set_context_reg(<wbr>sctx, R_028C44_PA_SC_BINNER_CNTL_0,<br>
+ SI_TRACKED_PA_SC_BINNER_CNTL_<wbr>0,<br>
+ S_028C44_BINNING_MODE(V_<wbr>028C44_DISABLE_BINNING_USE_<wbr>LEGACY_SC) |<br>
+ S_028C44_DISABLE_START_OF_<wbr>PRIM(1));<br>
+ radeon_opt_set_context_reg(<wbr>sctx, R_028060_DB_DFSM_CONTROL,<br>
+ SI_TRACKED_DB_DFSM_CONTROL,<br>
+ S_028060_PUNCHOUT_MODE(V_<wbr>028060_FORCE_OFF));<br>
}<br>
<br>
void si_emit_dpbb_state(struct si_context *sctx)<br>
@@ -431,18 +431,20 @@ void si_emit_dpbb_state(struct si_context *sctx)<br>
if (bin_size.y >= 32)<br>
bin_size_extend.y = util_logbase2(bin_size.y) - 5;<br>
<br>
- struct radeon_winsys_cs *cs = sctx->gfx_cs;<br>
- radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,<br>
- S_028C44_BINNING_MODE(V_<wbr>028C44_BINNING_ALLOWED) |<br>
- S_028C44_BIN_SIZE_X(bin_size.x == 16) |<br>
- S_028C44_BIN_SIZE_Y(bin_size.y == 16) |<br>
- S_028C44_BIN_SIZE_X_EXTEND(<wbr>bin_size_extend.x) |<br>
- S_028C44_BIN_SIZE_Y_EXTEND(<wbr>bin_size_extend.y) |<br>
- S_028C44_CONTEXT_STATES_PER_<wbr>BIN(context_states_per_bin) |<br>
- S_028C44_PERSISTENT_STATES_<wbr>PER_BIN(persistent_states_per_<wbr>bin) |<br>
- S_028C44_DISABLE_START_OF_<wbr>PRIM(disable_start_of_prim) |<br>
- S_028C44_FPOVS_PER_BATCH(<wbr>fpovs_per_batch) |<br>
- S_028C44_OPTIMAL_BIN_<wbr>SELECTION(1));<br>
- radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,<br>
- S_028060_PUNCHOUT_MODE(<wbr>punchout_mode));<br>
+ radeon_opt_set_context_reg(<br>
+ sctx, R_028C44_PA_SC_BINNER_CNTL_0,<br>
+ SI_TRACKED_PA_SC_BINNER_CNTL_<wbr>0,<br>
+ S_028C44_BINNING_MODE(V_<wbr>028C44_BINNING_ALLOWED) |<br>
+ S_028C44_BIN_SIZE_X(bin_size.x == 16) |<br>
+ S_028C44_BIN_SIZE_Y(bin_size.y == 16) |<br>
+ S_028C44_BIN_SIZE_X_EXTEND(<wbr>bin_size_extend.x) |<br>
+ S_028C44_BIN_SIZE_Y_EXTEND(<wbr>bin_size_extend.y) |<br>
+ S_028C44_CONTEXT_STATES_PER_<wbr>BIN(context_states_per_bin) |<br>
+ S_028C44_PERSISTENT_STATES_<wbr>PER_BIN(persistent_states_per_<wbr>bin) |<br>
+ S_028C44_DISABLE_START_OF_<wbr>PRIM(disable_start_of_prim) |<br>
+ S_028C44_FPOVS_PER_BATCH(<wbr>fpovs_per_batch) |<br>
+ S_028C44_OPTIMAL_BIN_<wbr>SELECTION(1));<br>
+ radeon_opt_set_context_reg(<wbr>sctx, R_028060_DB_DFSM_CONTROL,<br>
+ SI_TRACKED_DB_DFSM_CONTROL,<br>
+ S_028060_PUNCHOUT_MODE(<wbr>punchout_mode));<br>
}<br>
<span class="HOEnZb"><font color="#888888">-- <br>
2.7.4<br>
<br>
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