<div dir="ltr">FWIW none of our released Vulkan games will be using these functions.</div><div class="gmail_extra"><br><div class="gmail_quote">On 29 June 2018 at 03:28, Dieter Nützel <span dir="ltr"><<a href="mailto:Dieter@nuetzel-hh.de" target="_blank">Dieter@nuetzel-hh.de</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Tested-by: Dieter Nützel <<a href="mailto:Dieter@nuetzel-hh.de" target="_blank">Dieter@nuetzel-hh.de</a>><br>
<br>
on RX 580 with F1 2017.<span class="HOEnZb"><font color="#888888"><br>
<br>
Dieter</font></span><div class="HOEnZb"><div class="h5"><br>
<br>
Am 28.06.2018 12:21, schrieb Samuel Pitoiset:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Always emitting a bottom-of-pipe event is quite dumb. Instead,<br>
start to optimize these functions by syncing PFP for the<br>
top-of-pipe and syncing ME for the post-index-fetch event.<br>
<br>
This can still be improved by emitting EOS events for<br>
syncing PS and CS stages.<br>
<br>
Signed-off-by: Samuel Pitoiset <<a href="mailto:samuel.pitoiset@gmail.com" target="_blank">samuel.pitoiset@gmail.com</a>><br>
---<br>
src/amd/vulkan/radv_cmd_buffe<wbr>r.c | 46 ++++++++++++++++++++++++++----<wbr>--<br>
1 file changed, 38 insertions(+), 8 deletions(-)<br>
<br>
diff --git a/src/amd/vulkan/radv_cmd_buff<wbr>er.c b/src/amd/vulkan/radv_cmd_buff<wbr>er.c<br>
index 074e9c4c7f..17385aace1 100644<br>
--- a/src/amd/vulkan/radv_cmd_buff<wbr>er.c<br>
+++ b/src/amd/vulkan/radv_cmd_buff<wbr>er.c<br>
@@ -4275,14 +4275,44 @@ static void write_event(struct radv_cmd_buffer<br>
*cmd_buffer,<br>
<br>
MAYBE_UNUSED unsigned cdw_max =<br>
radeon_check_space(cmd_buffer-<wbr>>device->ws, cs, 18);<br>
<br>
- /* TODO: this is overkill. Probably should figure something out from<br>
- * the stage mask. */<br>
-<br>
- si_cs_emit_write_event_eop(<wbr>cs,<br>
- cmd_buffer->device->physical_d<wbr>evice->rad_info.chip_class,<br>
- radv_cmd_buffer_uses_mec(cmd_b<wbr>uffer),<br>
- V_028A90_BOTTOM_OF_PIPE_TS, 0,<br>
- EOP_DATA_SEL_VALUE_32BIT, va, 2, value);<br>
+ /* Flags that only require a top-of-pipe event. */<br>
+ static const VkPipelineStageFlags top_of_pipe_flags =<br>
+ VK_PIPELINE_STAGE_TOP_OF_<wbr>PIPE_BIT;<br>
+<br>
+ /* Flags that only require a post-index-fetch event. */<br>
+ static const VkPipelineStageFlags post_index_fetch_flags =<br>
+ top_of_pipe_flags |<br>
+ VK_PIPELINE_STAGE_DRAW_INDIRE<wbr>CT_BIT |<br>
+ VK_PIPELINE_STAGE_VERTEX_INPU<wbr>T_BIT;<br>
+<br>
+ /* TODO: Emit EOS events for syncing PS/CS stages. */<br>
+<br>
+ if (!(stageMask & ~top_of_pipe_flags)) {<br>
+ /* Just need to sync the PFP engine. */<br>
+ radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));<br>
+ radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |<br>
+ S_370_WR_CONFIRM(1) |<br>
+ S_370_ENGINE_SEL(V_370_PFP));<br>
+ radeon_emit(cs, va);<br>
+ radeon_emit(cs, va >> 32);<br>
+ radeon_emit(cs, value);<br>
+ } else if (!(stageMask & ~post_index_fetch_flags)) {<br>
+ /* Sync ME because PFP reads index and indirect buffers. */<br>
+ radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));<br>
+ radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |<br>
+ S_370_WR_CONFIRM(1) |<br>
+ S_370_ENGINE_SEL(V_370_ME));<br>
+ radeon_emit(cs, va);<br>
+ radeon_emit(cs, va >> 32);<br>
+ radeon_emit(cs, value);<br>
+ } else {<br>
+ /* Otherwise, sync all prior GPU work using an EOP event. */<br>
+ si_cs_emit_write_event_eop(<wbr>cs,<br>
+ cmd_buffer->device->physical_d<wbr>evice->rad_info.chip_class,<br>
+ radv_cmd_buffer_uses_mec(cmd_b<wbr>uffer),<br>
+ V_028A90_BOTTOM_OF_PIPE_TS, 0,<br>
+ EOP_DATA_SEL_VALUE_32BIT, va, 2, value);<br>
+ }<br>
<br>
assert(cmd_buffer->cs->cdw <= cdw_max);<br>
}<br>
</blockquote></div></div><div class="HOEnZb"><div class="h5">
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