<div dir="auto">Loads require barriers, while movs don't. I believe that's why the blob prefers 32-bit loads, and we do too. Why change it?</div><br><div class="gmail_quote"><div dir="ltr">On Thu, Jul 5, 2018, 06:21 Rhys Perry <<a href="mailto:pendingchaos02@gmail.com">pendingchaos02@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Seems to increase GPR count by a few in some shaders, but also decreases<br>
instruction count by a bit.<br>
<br>
This should only combine them when a mov can not be used (when the load<br>
is indirect).<br>
<br>
total instructions in shared programs : 5804448 -> 5754102 (-0.87%)<br>
total gprs used in shared programs : 670065 -> 672540 (0.37%)<br>
total shared used in shared programs : 548832 -> 548832 (0.00%)<br>
total local used in shared programs : 21068 -> 21068 (0.00%)<br>
<br>
local shared gpr inst bytes<br>
helped 0 0 194 4124 4124<br>
hurt 0 0 1579 97 97<br>
<br>
Signed-off-by: Rhys Perry <<a href="mailto:pendingchaos02@gmail.com" target="_blank" rel="noreferrer">pendingchaos02@gmail.com</a>><br>
---<br>
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 5 +++++<br>
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 9 ++-------<br>
2 files changed, 7 insertions(+), 7 deletions(-)<br>
<br>
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp<br>
index 39177bd044..6785082b5a 100644<br>
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp<br>
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp<br>
@@ -2538,6 +2538,11 @@ MemoryOpt::combineLd(Record *rec, Instruction *ld)<br>
// for compute indirect loads are not guaranteed to be aligned<br>
if (prog->getType() == Program::TYPE_COMPUTE && rec->rel[0])<br>
return false;<br>
+ // don't combine non-indirect constant loads since OP_LOAD is a<br>
+ // inefficient way of doing them<br>
+ if (prog->getTarget()->getChipset() >= NVISA_GM107_CHIPSET &&<br>
+ ld->getSrc(0)->reg.file == FILE_MEMORY_CONST && !ld->src(0).isIndirect(0))<br>
+ return false;<br>
<br>
assert(sizeRc + sizeLd <= 16 && offRc != offLd);<br>
<br>
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp<br>
index 7e059235f4..514e1b3723 100644<br>
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp<br>
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp<br>
@@ -429,13 +429,8 @@ TargetNVC0::isAccessSupported(DataFile file, DataType ty) const<br>
{<br>
if (ty == TYPE_NONE)<br>
return false;<br>
- if (file == FILE_MEMORY_CONST) {<br>
- if (getChipset() >= NVISA_GM107_CHIPSET)<br>
- return typeSizeof(ty) <= 4;<br>
- else<br>
- if (getChipset() >= NVISA_GK104_CHIPSET) // wrong encoding ?<br>
- return typeSizeof(ty) <= 8;<br>
- }<br>
+ if (file == FILE_MEMORY_CONST && getChipset() >= NVISA_GK104_CHIPSET) // wrong encoding ?<br>
+ return typeSizeof(ty) <= 8;<br>
if (ty == TYPE_B96)<br>
return false;<br>
return true;<br>
-- <br>
2.14.4<br>
<br>
</blockquote></div>