<div dir="ltr">This appears to hang broadwell; we should probably think twice before enabling it so broadly. I'll adjust it to be gen9 only or we can just can the patch entirely.<br></div><br><div class="gmail_quote"><div dir="ltr">On Tue, Aug 21, 2018 at 8:58 PM Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Known to fix nothing whatsoever but it's in the docs.<br>
---<br>
src/intel/vulkan/genX_cmd_buffer.c | 9 +++++++++<br>
1 file changed, 9 insertions(+)<br>
<br>
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c<br>
index 18f80e8d1bd..75b3dd54275 100644<br>
--- a/src/intel/vulkan/genX_cmd_buffer.c<br>
+++ b/src/intel/vulkan/genX_cmd_buffer.c<br>
@@ -1743,6 +1743,9 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)<br>
}<br>
<br>
if (bits & ANV_PIPE_INVALIDATE_BITS) {<br>
+ if (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)<br>
+ anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe);<br>
+<br>
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {<br>
pipe.StateCacheInvalidationEnable =<br>
bits & ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;<br>
@@ -1754,6 +1757,12 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)<br>
bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;<br>
pipe.InstructionCacheInvalidateEnable =<br>
bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT;<br>
+<br>
+ if (pipe.VFCacheInvalidationEnable) {<br>
+ pipe.PostSyncOperation = WriteImmediateData;<br>
+ pipe.Address =<br>
+ (struct anv_address) { &cmd_buffer->device->workaround_bo, 0 };<br>
+ }<br>
}<br>
<br>
bits &= ~ANV_PIPE_INVALIDATE_BITS;<br>
-- <br>
2.17.1<br>
<br>
</blockquote></div>