<div dir="ltr"><div>Hi Sonny,</div><div><br></div><div>Can you send a version that only does >= CIK && drm_major == 3? It's equivalent to your version but simpler.</div><div><br></div><div>Marek<br></div></div><br><div class="gmail_quote"><div dir="ltr">On Thu, Oct 18, 2018 at 12:40 PM Jiang, Sonny <<a href="mailto:Sonny.Jiang@amd.com">Sonny.Jiang@amd.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Signed-off-by: Sonny Jiang <<a href="mailto:sonny.jiang@amd.com" target="_blank">sonny.jiang@amd.com</a>><br>
---<br>
src/gallium/drivers/radeonsi/si_pipe.c | 7 +++++--<br>
src/gallium/drivers/radeonsi/si_state.c | 5 +++--<br>
2 files changed, 8 insertions(+), 4 deletions(-)<br>
<br>
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c<br>
index 9d25748df4..3da44483d6 100644<br>
--- a/src/gallium/drivers/radeonsi/si_pipe.c<br>
+++ b/src/gallium/drivers/radeonsi/si_pipe.c<br>
@@ -991,8 +991,11 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,<br>
}<br>
<br>
/* The mere presense of CLEAR_STATE in the IB causes random GPU hangs<br>
- * on SI. */<br>
- sscreen->has_clear_state = sscreen->info.chip_class >= CIK;<br>
+ * on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc.<br>
+ * SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/<br>
+ sscreen->has_clear_state = sscreen->info.chip_class > CIK ||<br>
+ (sscreen->info.chip_class == CIK &&<br>
+ sscreen->info.drm_major == 3);<br>
<br>
sscreen->has_distributed_tess =<br>
sscreen->info.chip_class >= VI &&<br>
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c<br>
index 8b2e6e57f4..ba84a5a42a 100644<br>
--- a/src/gallium/drivers/radeonsi/si_state.c<br>
+++ b/src/gallium/drivers/radeonsi/si_state.c<br>
@@ -4899,8 +4899,9 @@ static void si_init_config(struct si_context *sctx)<br>
bool has_clear_state = sscreen->has_clear_state;<br>
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);<br>
<br>
- /* Only SI can disable CLEAR_STATE for now. */<br>
- assert(has_clear_state || sscreen->info.chip_class == SI);<br>
+ /* SI, radeon kernel CIK disabled CLEAR_STATE. */<br>
+ assert(has_clear_state || sscreen->info.chip_class == SI ||<br>
+ (sscreen->info.chip_class == CIK && sscreen->info.drm_major != 3));<br>
<br>
if (!pm4)<br>
return;<br>
-- <br>
2.17.1<br>
<br>
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</blockquote></div>