<div dir="ltr"><div class="gmail_quote"><div dir="ltr">On Thu, Oct 25, 2018 at 6:25 PM <<a href="mailto:nanleychery@gmail.com">nanleychery@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Nanley Chery <<a href="mailto:nanley.g.chery@intel.com" target="_blank">nanley.g.chery@intel.com</a>><br>
<br>
Follow the restriction of making sure the clear value is between the min<br>
and max values defined in CC_VIEWPORT. Avoids a simulator warning for<br>
some piglit tests, one of them being:<br>
<br>
./bin/depthstencil-render-miplevels 146 d=z32f_s8<br>
<br>
Jason found this to make a GPU hang go away on SKL.<br></blockquote><div><br></div><div>It wasn't really hangs. It was just incorrect clearing. The hangs may be related but I have no proof of that. With the commit message adjusted accordingly, this patch is</div><div><br></div><div>Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>></div><div>Tested-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Fixes: 09948151ab1d5184b4dd9052bb1f710fa1e00a7b<br>
("intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP")<br>
---<br>
src/intel/blorp/blorp_genX_exec.h | 14 ++++++++++++++<br>
1 file changed, 14 insertions(+)<br>
<br>
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h<br>
index 50341ab0ecf..7a8c45dbee5 100644<br>
--- a/src/intel/blorp/blorp_genX_exec.h<br>
+++ b/src/intel/blorp/blorp_genX_exec.h<br>
@@ -1628,6 +1628,20 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,<br>
*/<br>
blorp_emit_3dstate_multisample(batch, params);<br>
<br>
+ /* From the BDW PRM Volume 7, Depth Buffer Clear:<br>
+ *<br>
+ * The clear value must be between the min and max depth values<br>
+ * (inclusive) defined in the CC_VIEWPORT. If the depth buffer format is<br>
+ * D32_FLOAT, then +/-DENORM values are also allowed.<br>
+ *<br>
+ * Set the bounds to match our hardware limits, [0.0, 1.0].<br>
+ */<br>
+ if (params->depth.enabled && params->hiz_op == ISL_AUX_OP_FAST_CLEAR) {<br>
+ assert(params->depth.clear_color.f32[0] >= 0.0f);<br>
+ assert(params->depth.clear_color.f32[0] <= 1.0f);<br>
+ blorp_emit_cc_viewport(batch);<br>
+ }<br>
+<br>
/* If we can't alter the depth stencil config and multiple layers are<br>
* involved, the HiZ op will fail. This is because the op requires that a<br>
* new config is emitted for each additional layer.<br>
-- <br>
2.19.0<br>
<br>
</blockquote></div></div>