<div dir="ltr"><div class="gmail_quote"><div dir="ltr">On Sat, Oct 27, 2018 at 8:03 PM Timothy Arceri <<a href="mailto:tarceri@itsqueeze.com">tarceri@itsqueeze.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Timothy Arceri <tarceri@localhost.localdomain><br>
<br>
Commit 8d8222461f9d7f49 caused substantially more URB messages in<br>
geometry and tessellation shaders (due to enabling<br>
nir_lower_io_to_scalar_early). This combines io again to avoid<br>
this regression while still allowing link time optimisation of<br>
components.<br>
<br>
Shader-db results (SKL):<br>
<br>
total instructions in shared programs: 13107449 -> 13104666 (-0.02%)<br>
instructions in affected programs: 304803 -> 302020 (-0.91%)<br>
helped: 1136<br>
HURT: 409<br>
<br>
total cycles in shared programs: 332066434 -> 332125306 (0.02%)<br>
cycles in affected programs: 70735188 -> 70794060 (0.08%)<br>
helped: 11797<br>
HURT: 13257<br>
<br>
LOST: 2<br>
GAINED: 1<br>
<br>
Most of the cycle/instruction changes is with fragment shaders.<br></blockquote><div><br></div><div>Why are we running it on fragment shaders? They don't benefit at all from vector I/O. For that matter, why does it affect them at all?</div><div><br></div><div>--Jason</div><div><br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Bugzilla: <a href="https://bugs.freedesktop.org/show_bug.cgi?id=107510" rel="noreferrer" target="_blank">https://bugs.freedesktop.org/show_bug.cgi?id=107510</a><br>
---<br>
src/intel/vulkan/anv_pipeline.c | 6 ++++++<br>
src/mesa/drivers/dri/i965/brw_link.cpp | 6 ++++++<br>
2 files changed, 12 insertions(+)<br>
<br>
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c<br>
index 7c9b1230115..63acb3cc25e 100644<br>
--- a/src/intel/vulkan/anv_pipeline.c<br>
+++ b/src/intel/vulkan/anv_pipeline.c<br>
@@ -1016,6 +1016,12 @@ anv_pipeline_compile_graphics(struct anv_pipeline *pipeline,<br>
<br>
void *stage_ctx = ralloc_context(NULL);<br>
<br>
+ if (nir_opt_vectorize_io(stages[s].nir)) {<br>
+ brw_nir_optimize(stages[s].nir, compiler,<br>
+ compiler->scalar_stage[stages[s].nir->info.stage],<br>
+ false);<br>
+ }<br>
+<br>
anv_pipeline_lower_nir(pipeline, stage_ctx, &stages[s], layout);<br>
<br>
const unsigned *code;<br>
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp<br>
index 2cbb1e0b879..0bcd73af04c 100644<br>
--- a/src/mesa/drivers/dri/i965/brw_link.cpp<br>
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp<br>
@@ -319,6 +319,12 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)<br>
<br>
struct gl_program *prog = shader->Program;<br>
<br>
+ if (nir_opt_vectorize_io(prog->nir)) {<br>
+ brw_nir_optimize(prog->nir, compiler,<br>
+ compiler->scalar_stage[prog->info.stage],<br>
+ false);<br>
+ }<br>
+<br>
_mesa_update_shader_textures_used(shProg, prog);<br>
<br>
brw_shader_gather_info(prog->nir, prog);<br>
-- <br>
2.17.2<br>
<br>
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</blockquote></div></div>