<div dir="ltr"><div>Down with 32-bit offsets!</div><div><br></div><div>Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br></div></div><br><div class="gmail_quote"><div dir="ltr">On Thu, Nov 29, 2018 at 2:24 AM Kenneth Graunke <<a href="mailto:kenneth@whitecape.org">kenneth@whitecape.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">In the softpin world, surface state base address may be a fixed 64-bit<br>
address (with no associated BO). It makes sense to store this in the<br>
offset field. But it needs to be the full size.<br>
<br>
We also update the clear color address to be consistently uint64_t<br>
everywhere so we can continue passing intel_miptree_get_clear_color<br>
a pointer to the blorp_address's offset field without type mismatches.<br>
---<br>
src/intel/blorp/blorp.h | 2 +-<br>
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +-<br>
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-<br>
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-<br>
4 files changed, 4 insertions(+), 4 deletions(-)<br>
<br>
diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h<br>
index ee343a4a6bb..1e22712602d 100644<br>
--- a/src/intel/blorp/blorp.h<br>
+++ b/src/intel/blorp/blorp.h<br>
@@ -91,8 +91,8 @@ void blorp_batch_finish(struct blorp_batch *batch);<br>
<br>
struct blorp_address {<br>
void *buffer;<br>
+ uint64_t offset;<br>
unsigned reloc_flags;<br>
- uint32_t offset;<br>
uint32_t mocs;<br>
};<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c<br>
index 4daa0e2add1..b067a174056 100644<br>
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c<br>
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c<br>
@@ -156,7 +156,7 @@ brw_emit_surface_state(struct brw_context *brw,<br>
struct isl_surf *aux_surf = NULL;<br>
uint64_t aux_offset = 0;<br>
struct brw_bo *clear_bo = NULL;<br>
- uint32_t clear_offset = 0;<br>
+ uint64_t clear_offset = 0;<br>
<br>
if (aux_usage != ISL_AUX_USAGE_NONE) {<br>
aux_surf = &mt->aux_buf->surf;<br>
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c<br>
index 8e50aabb3b4..a679ddf3e48 100644<br>
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c<br>
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c<br>
@@ -3865,7 +3865,7 @@ intel_miptree_get_clear_color(const struct gen_device_info *devinfo,<br>
const struct intel_mipmap_tree *mt,<br>
enum isl_format view_format, bool sampling,<br>
struct brw_bo **clear_color_bo,<br>
- uint32_t *clear_color_offset)<br>
+ uint64_t *clear_color_offset)<br>
{<br>
assert(mt->aux_buf);<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h<br>
index b0333655ad5..21beeded92a 100644<br>
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h<br>
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h<br>
@@ -714,7 +714,7 @@ intel_miptree_get_clear_color(const struct gen_device_info *devinfo,<br>
const struct intel_mipmap_tree *mt,<br>
enum isl_format view_format, bool sampling,<br>
struct brw_bo **clear_color_bo,<br>
- uint32_t *clear_color_offset);<br>
+ uint64_t *clear_color_offset);<br>
<br>
<br>
static inline int<br>
-- <br>
2.19.1<br>
<br>
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</blockquote></div>