<html dir="ltr"><head></head><body style="text-align:left; direction:ltr;"><div>Yeah, maybe. I'll do that.</div><div><br></div><div>On Fri, 2018-12-07 at 11:31 -0600, Jason Ekstrand wrote:</div><blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex"><div dir="ltr">I think it's probably less code to just make a separate 16-bit case.<br></div><br><div class="gmail_quote"><div dir="ltr">On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga <<a href="mailto:itoral@igalia.com">itoral@igalia.com</a>> wrote:<br></div><blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">---<br>
src/intel/compiler/brw_fs_nir.cpp | 27 +++++++++++++++++++++------<br>
1 file changed, 21 insertions(+), 6 deletions(-)<br>
<br>
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp<br>
index 3eba8a478f5..559b55a0f84 100644<br>
--- a/src/intel/compiler/brw_fs_nir.cpp<br>
+++ b/src/intel/compiler/brw_fs_nir.cpp<br>
@@ -938,14 +938,29 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)<br>
* Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not<br>
* zero.<br>
*/<br>
- bld.CMP(bld.null_reg_f(), op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ);<br>
+ fs_reg zero, one_mask, sign_mask;<br>
+ brw_reg_type reg_type;<br>
+ if (type_sz(op[0].type) == 4) {<br>
+ zero = brw_imm_f(0.0f);<br>
+ one_mask = brw_imm_ud(0x3f800000);<br>
+ sign_mask = brw_imm_ud(0x80000000);<br>
+ reg_type = BRW_REGISTER_TYPE_UD;<br>
+ } else {<br>
+ assert(type_sz(op[0].type) == 2);<br>
+ zero = retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF);<br>
+ one_mask = brw_imm_uw(0x3c00);<br>
+ sign_mask = brw_imm_uw(0x8000);<br>
+ reg_type = BRW_REGISTER_TYPE_UW;<br>
+ }<br>
+<br>
+ bld.CMP(bld.null_reg_f(), op[0], zero, BRW_CONDITIONAL_NZ);<br>
<br>
- fs_reg result_int = retype(result, BRW_REGISTER_TYPE_UD);<br>
- op[0].type = BRW_REGISTER_TYPE_UD;<br>
- result.type = BRW_REGISTER_TYPE_UD;<br>
- bld.AND(result_int, op[0], brw_imm_ud(0x80000000u));<br>
+ fs_reg result_int = retype(result, reg_type);<br>
+ op[0].type = reg_type;<br>
+ result.type = reg_type;<br>
+ bld.AND(result_int, op[0], sign_mask);<br>
<br>
- inst = bld.OR(result_int, result_int, brw_imm_ud(0x3f800000u));<br>
+ inst = bld.OR(result_int, result_int, one_mask);<br>
inst->predicate = BRW_PREDICATE_NORMAL;<br>
} else {<br>
/* For doubles we do the same but we need to consider:<br>
</blockquote></div></blockquote></body></html>