<div dir="ltr"><div>I prefer Nicolai's patch because it's shorter and doesn't need driver changes.</div><div><br></div><div>Reviewed-by: Marek Olšák <<a href="mailto:marek.olsak@amd.com">marek.olsak@amd.com</a>></div><div><br></div><div>Marek<br></div></div><br><div class="gmail_quote"><div dir="ltr">On Tue, Dec 18, 2018 at 12:50 PM Haehnle, Nicolai <<a href="mailto:Nicolai.Haehnle@amd.com">Nicolai.Haehnle@amd.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">On 18.12.18 18:36, Bas Nieuwenhuizen wrote:<br>
> Hi Nicolai,<br>
> <br>
> I happened to be writing something similar which also fixes up radv to<br>
> never render to those surfaces as r32g32b32a32:<br>
> <a href="https://patchwork.freedesktop.org/series/54172/" rel="noreferrer" target="_blank">https://patchwork.freedesktop.org/series/54172/</a> I can split out the<br>
> radv specific stuff and this one is r-b after than.<br>
<br>
Oh, I missed that, sorry. I don't particularly care about which approach <br>
to this is taken.<br>
<br>
Cheers,<br>
Nicolai<br>
<br>
<br>
<br>
> <br>
> Thanks,<br>
> Bas<br>
> <br>
> On Tue, Dec 18, 2018 at 5:37 PM Nicolai Hähnle <<a href="mailto:nhaehnle@gmail.com" target="_blank">nhaehnle@gmail.com</a>> wrote:<br>
>><br>
>> From: Nicolai Hähnle <<a href="mailto:nicolai.haehnle@amd.com" target="_blank">nicolai.haehnle@amd.com</a>><br>
>><br>
>> In the gfx9 addrlib, this bit has been clarified as meaning that<br>
>> the surface can be used as a color buffer (render target).<br>
>><br>
>> Setting this for compressed surfaces triggers a workaround that<br>
>> is only required for surfaces that can be render targets, and ends<br>
>> up breaking the 16-byte-per-block case.<br>
>><br>
>> Fixes dEQP-VK.pipeline.image.suballocation.sampling_type.combined.view_type.3d.format.etc2_r8g8b8a8_srgb_block.count_1.size.11x11x11 and others<br>
>><br>
>> Note that there are other related bits which we don't set as intended<br>
>> by the interface, notably the 'unordered' bit, which is meant to<br>
>> indicate use as a shader image. It may be worth cleaning that up at some<br>
>> point after proper testing.<br>
>><br>
>> Reported-by: Samuel Pitoiset <<a href="mailto:samuel.pitoiset@gmail.com" target="_blank">samuel.pitoiset@gmail.com</a>><br>
>> Fixes: 776b9113656 ("amd/addrlib: update Mesa's copy of addrlib")<br>
>> ---<br>
>> src/amd/common/ac_surface.c | 5 ++---<br>
>> 1 file changed, 2 insertions(+), 3 deletions(-)<br>
>><br>
>> diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c<br>
>> index d8d927ee1c5..d647bd523f9 100644<br>
>> --- a/src/amd/common/ac_surface.c<br>
>> +++ b/src/amd/common/ac_surface.c<br>
>> @@ -1405,25 +1405,24 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,<br>
>> case 16:<br>
>> assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));<br>
>> AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;<br>
>> break;<br>
>> default:<br>
>> assert(0);<br>
>> }<br>
>> AddrSurfInfoIn.bpp = surf->bpe * 8;<br>
>> }<br>
>><br>
>> - AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);<br>
>> + AddrSurfInfoIn.flags.color = !compressed && !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);<br>
>> AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;<br>
>> AddrSurfInfoIn.flags.display = get_display_flag(config, surf);<br>
>> - /* flags.texture currently refers to TC-compatible HTILE */<br>
>> - AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||<br>
>> + AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color || compressed ||<br>
>> surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;<br>
>> AddrSurfInfoIn.flags.opt4space = 1;<br>
>><br>
>> AddrSurfInfoIn.numMipLevels = config->info.levels;<br>
>> AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);<br>
>> AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;<br>
>><br>
>> if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))<br>
>> AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);<br>
>><br>
>> --<br>
>> 2.19.1<br>
>><br>
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</blockquote></div>