<div dir="ltr"><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, Feb 13, 2019 at 3:30 PM Eduardo Lima Mitev <<a href="mailto:elima@igalia.com">elima@igalia.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">ir3 compiler has an integer multiply-add instruction (MAD_S24)<br>
that is used for different offset calculations in the backend.<br>
Since we intend to move some of these calculations to NIR, we need<br>
a new ALU op that can directly represent it.<br>
---<br>
src/compiler/nir/nir_opcodes.py | 16 ++++++++++++++++<br>
1 file changed, 16 insertions(+)<br>
<br>
diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py<br>
index d32005846a6..abbb3627a33 100644<br>
--- a/src/compiler/nir/nir_opcodes.py<br>
+++ b/src/compiler/nir/nir_opcodes.py<br>
@@ -892,3 +892,19 @@ dst.w = src3.x;<br>
""")<br>
<br>
<br>
+# Freedreno-specific opcode that maps directly to ir3_MAD_S24.<br>
+# It is emitted by ir3_nir_lower_io_offsets pass when computing<br>
+# byte-offsets for image store and atomics.<br>
+#<br>
+# The nir_algebraic expression below is: get 23 bits of the<br>
+# two factors as unsigned and multiply them. If either of the<br>
+# two was negative, invert sign of the product. Then add it src2.<br>
+# @FIXME: I suspect there is a simpler expression for this.<br>
+triop("imad24_ir3", tint, """<br></blockquote><div><br></div><div>I doubt you really want this to be a variable bit-size opcode. Maybe tint32?<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
+unsigned f0 = ((unsigned) src0) & 0x7fffff;<br>
+unsigned f1 = ((unsigned) src1) & 0x7fffff;<br>
+dst = f0 * f1;<br>
+if (src0 * src1 < 0)<br>
+ dst = -dst;<br>
+dst += src2;<br>
+""")<br>
-- <br>
2.20.1<br>
<br>
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