<div dir="ltr"><div>Yup.Â Not getting used at all.</div><div> </div><div>Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>> </div></div> <div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Mar 14, 2019 at 12:10 PM Rafael Antognolli <<a href="mailto:rafael.antognolli@intel.com">rafael.antognolli@intel.com</a>> wrote: </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">It seems pretty useless nowadays. --- Â src/mesa/drivers/dri/i965/brw_blorp.c | 36 +++++++++------------------ Â 1 file changed, 12 insertions(+), 24 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 97a5f6a9937..e09a8cef762 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -125,8 +125,7 @@ blorp_surf_for_miptree(struct brw_context *brw, Â Â Â Â Â Â Â Â Â Â Â Â enum isl_aux_usage aux_usage, Â Â Â Â Â Â Â Â Â Â Â Â bool is_render_target, Â Â Â Â Â Â Â Â Â Â Â Â unsigned *level, -Â Â Â Â Â Â Â Â Â Â Â Â unsigned start_layer, unsigned num_layers, -Â Â Â Â Â Â Â Â Â Â Â Â struct isl_surf tmp_surfs[1]) +Â Â Â Â Â Â Â Â Â Â Â Â unsigned start_layer, unsigned num_layers) Â { Â Â const struct gen_device_info *devinfo = &brw->screen->devinfo; @@ -406,12 +405,11 @@ brw_blorp_blit_miptrees(struct brw_context *brw, Â Â intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â dst_aux_usage, dst_clear_supported); -Â Â struct isl_surf tmp_surfs[2]; Â Â struct blorp_surf src_surf, dst_surf; Â Â blorp_surf_for_miptree(brw, &src_surf, src_mt, src_aux_usage, false, -Â Â Â Â Â Â Â Â Â Â Â Â Â &src_level, src_layer, 1, &tmp_surfs[0]); +Â Â Â Â Â Â Â Â Â Â Â Â Â &src_level, src_layer, 1); Â Â blorp_surf_for_miptree(brw, &dst_surf, dst_mt, dst_aux_usage, true, -Â Â Â Â Â Â Â Â Â Â Â Â Â &dst_level, dst_layer, 1, &tmp_surfs[1]); +Â Â Â Â Â Â Â Â Â Â Â Â Â &dst_level, dst_layer, 1); Â Â struct isl_swizzle src_isl_swizzle = { Â Â Â Â .r = swizzle_to_scs(GET_SWZ(src_swizzle, 0)), @@ -497,12 +495,11 @@ brw_blorp_copy_miptrees(struct brw_context *brw, Â Â intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â dst_aux_usage, dst_clear_supported); -Â Â struct isl_surf tmp_surfs[2]; Â Â struct blorp_surf src_surf, dst_surf; Â Â blorp_surf_for_miptree(brw, &src_surf, src_mt, src_aux_usage, false, -Â Â Â Â Â Â Â Â Â Â Â Â Â &src_level, src_layer, 1, &tmp_surfs[0]); +Â Â Â Â Â Â Â Â Â Â Â Â Â &src_level, src_layer, 1); Â Â blorp_surf_for_miptree(brw, &dst_surf, dst_mt, dst_aux_usage, true, -Â Â Â Â Â Â Â Â Â Â Â Â Â &dst_level, dst_layer, 1, &tmp_surfs[1]); +Â Â Â Â Â Â Â Â Â Â Â Â Â &dst_level, dst_layer, 1); Â Â /* The hardware seems to have issues with having a two different format Â Â Â * views of the same texture in the sampler cache at the same time.Â It's @@ -1300,10 +1297,9 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, Â Â Â Â Â Â irb->mt, irb->mt_level, irb->mt_layer, num_layers); Â Â Â Â /* We can't setup the blorp_surf until we've allocated the MCS above */ -Â Â Â struct isl_surf isl_tmp[2]; Â Â Â Â struct blorp_surf surf; Â Â Â Â blorp_surf_for_miptree(brw, &surf, irb->mt, irb->mt->aux_usage, true, -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &level, irb->mt_layer, num_layers, isl_tmp); +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &level, irb->mt_layer, num_layers); Â Â Â Â /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)": Â Â Â Â * @@ -1346,10 +1342,9 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, Â Â Â Â intel_miptree_prepare_render(brw, irb->mt, level, irb->mt_layer, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â num_layers, aux_usage); -Â Â Â struct isl_surf isl_tmp[2]; Â Â Â Â struct blorp_surf surf; Â Â Â Â blorp_surf_for_miptree(brw, &surf, irb->mt, aux_usage, true, -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &level, irb->mt_layer, num_layers, isl_tmp); +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &level, irb->mt_layer, num_layers); Â Â Â Â union isl_color_value clear_color; Â Â Â Â memcpy(clear_color.f32, ctx->Color.ClearColor.f, sizeof(float) * 4); @@ -1442,7 +1437,6 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw, Â Â Â Â return; Â Â uint32_t level, start_layer, num_layers; -Â Â struct isl_surf isl_tmp[4]; Â Â struct blorp_surf depth_surf, stencil_surf; Â Â struct intel_mipmap_tree *depth_mt = NULL; @@ -1459,8 +1453,7 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw, Â Â Â Â unsigned depth_level = level; Â Â Â Â blorp_surf_for_miptree(brw, &depth_surf, depth_mt, depth_mt->aux_usage, -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â true, &depth_level, start_layer, num_layers, -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &isl_tmp[0]); +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â true, &depth_level, start_layer, num_layers); Â Â Â Â assert(depth_level == level); Â Â } @@ -1489,8 +1482,7 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw, Â Â Â Â unsigned stencil_level = level; Â Â Â Â blorp_surf_for_miptree(brw, &stencil_surf, stencil_mt, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ISL_AUX_USAGE_NONE, true, -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &stencil_level, start_layer, num_layers, -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &isl_tmp[2]); +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &stencil_level, start_layer, num_layers); Â Â } Â Â assert((mask & BUFFER_BIT_DEPTH) || stencil_mask); @@ -1525,11 +1517,9 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt, Â Â const mesa_format format = _mesa_get_srgb_format_linear(mt->format); -Â Â struct isl_surf isl_tmp[1]; Â Â struct blorp_surf surf; Â Â blorp_surf_for_miptree(brw, &surf, mt, mt->aux_usage, true, -Â Â Â Â Â Â Â Â Â Â Â Â Â &level, layer, 1 /* num_layers */, -Â Â Â Â Â Â Â Â Â Â Â Â Â isl_tmp); +Â Â Â Â Â Â Â Â Â Â Â Â Â &level, layer, 1 /* num_layers */); Â Â /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)": Â Â Â * @@ -1570,11 +1560,10 @@ brw_blorp_mcs_partial_resolve(struct brw_context *brw, Â Â const mesa_format format = _mesa_get_srgb_format_linear(mt->format); Â Â enum isl_format isl_format = brw_blorp_to_isl_format(brw, format, true); -Â Â struct isl_surf isl_tmp[1]; Â Â struct blorp_surf surf; Â Â uint32_t level = 0; Â Â blorp_surf_for_miptree(brw, &surf, mt, ISL_AUX_USAGE_MCS, true, -Â Â Â Â Â Â Â Â Â Â Â Â Â &level, start_layer, num_layers, isl_tmp); +Â Â Â Â Â Â Â Â Â Â Â Â Â &level, start_layer, num_layers); Â Â struct blorp_batch batch; Â Â blorp_batch_init(&brw->blorp, &batch, brw, 0); @@ -1667,10 +1656,9 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, Â Â assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->aux_buf); -Â Â struct isl_surf isl_tmp[2]; Â Â struct blorp_surf surf; Â Â blorp_surf_for_miptree(brw, &surf, mt, ISL_AUX_USAGE_HIZ, true, -Â Â Â Â Â Â Â Â Â Â Â Â Â &level, start_layer, num_layers, isl_tmp); +Â Â Â Â Â Â Â Â Â Â Â Â Â &level, start_layer, num_layers); Â Â struct blorp_batch batch; Â Â blorp_batch_init(&brw->blorp, &batch, brw, -- 2.17.2 _______________________________________________ mesa-dev mailing list <a href="mailto:mesa-dev@lists.freedesktop.org" target="_blank">mesa-dev@lists.freedesktop.org</a> <a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev" rel="noreferrer" target="_blank">https://lists.freedesktop.org/mailman/listinfo/mesa-dev</a></blockquote></div>