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    <div class="moz-cite-prefix">On 3/28/19 4:45 PM, Jason Ekstrand
      wrote:<br>
    </div>
    <blockquote type="cite"
cite="mid:CAOFGe95ob3YzLpNVSazM1YTjQ+MkyP2RqQvKEC4W7oNXcKN8TA@mail.gmail.com">
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          <div dir="ltr" class="gmail_attr">On Thu, Mar 28, 2019 at
            10:27 AM Samuel Pitoiset <<a
              href="mailto:samuel.pitoiset@gmail.com"
              moz-do-not-send="true">samuel.pitoiset@gmail.com</a>>
            wrote:<br>
          </div>
          <blockquote class="gmail_quote" style="margin:0px 0px 0px
            0.8ex;border-left:1px solid
            rgb(204,204,204);padding-left:1ex">
            <div bgcolor="#FFFFFF">
              <p>Calling it after the first call of radv_optimize_nir()
                is worse.</p>
            </div>
          </blockquote>
          <div><br>
          </div>
          <div>Ugh.... Do we know why?  I mean, it does emit the offset
            calculations in a slightly different order but I wouldn't
            expect it to hurt this bad. :-/<br>
          </div>
        </div>
      </div>
    </blockquote>
    I don't know exactly what the problem is, I will investigate soon.<br>
    <blockquote type="cite"
cite="mid:CAOFGe95ob3YzLpNVSazM1YTjQ+MkyP2RqQvKEC4W7oNXcKN8TA@mail.gmail.com">
      <div dir="ltr">
        <div class="gmail_quote">
          <div> </div>
          <blockquote class="gmail_quote" style="margin:0px 0px 0px
            0.8ex;border-left:1px solid
            rgb(204,204,204);padding-left:1ex">
            <div bgcolor="#FFFFFF">
              <p>27747 shaders in 14347 tests<br>
                Totals:<br>
                SGPRS: 1248039 -> 1248031 (-0.00 %)<br>
                VGPRS: 868360 -> 868772 (0.05 %)<br>
                Spilled SGPRs: 24108 -> 24134 (0.11 %)<br>
                Spilled VGPRs: 122 -> 122 (0.00 %)<br>
                Private memory VGPRs: 0 -> 0 (0.00 %)<br>
                Scratch size: 128 -> 128 (0.00 %) dwords per thread<br>
                Code Size: 46282020 -> 46336692 (0.12 %) bytes<br>
                LDS: 770 -> 770 (0.00 %) blocks<br>
                Max Waves: 199898 -> 199871 (-0.01 %)<br>
                Wait states: 0 -> 0 (0.00 %)<br>
                <br>
                Totals from affected shaders:<br>
                SGPRS: 52848 -> 52840 (-0.02 %)<br>
                VGPRS: 47472 -> 47884 (0.87 %)<br>
                Spilled SGPRs: 5079 -> 5105 (0.51 %)<br>
                Spilled VGPRs: 0 -> 0 (0.00 %)<br>
                Private memory VGPRs: 0 -> 0 (0.00 %)<br>
                Scratch size: 0 -> 0 (0.00 %) dwords per thread<br>
                Code Size: 4760924 -> 4815596 (1.15 %) bytes<br>
                LDS: 26 -> 26 (0.00 %) blocks<br>
                Max Waves: 3084 -> 3057 (-0.88 %)<br>
                Wait states: 0 -> 0 (0.00 %)<br>
              </p>
              <div class="gmail-m_2854222148469722852moz-cite-prefix">On
                3/28/19 3:08 PM, Jason Ekstrand wrote:<br>
              </div>
              <blockquote type="cite">
                <div dir="ltr">
                  <div class="gmail_quote">
                    <div dir="ltr" class="gmail_attr">On Wed, Mar 27,
                      2019 at 4:13 AM Samuel Pitoiset <<a
                        href="mailto:samuel.pitoiset@gmail.com"
                        target="_blank" moz-do-not-send="true">samuel.pitoiset@gmail.com</a>>
                      wrote:<br>
                    </div>
                    <blockquote class="gmail_quote" style="margin:0px
                      0px 0px 0.8ex;border-left:1px solid
                      rgb(204,204,204);padding-left:1ex">This helps few
                      compute shaders, mostly for F12017.<br>
                      <br>
                      27670 shaders in 14347 tests<br>
                      Totals:<br>
                      SGPRS: 1231173 -> 1231173 (0.00 %)<br>
                      VGPRS: 866056 -> 865928 (-0.01 %)<br>
                      Spilled SGPRs: 24201 -> 24201 (0.00 %)<br>
                      Code Size: 46137040 -> 46144868 (0.02 %) bytes<br>
                      Max Waves: 232287 -> 232302 (0.01 %)<br>
                      <br>
                      Totals from affected shaders:<br>
                      SGPRS: 24624 -> 24624 (0.00 %)<br>
                      VGPRS: 25960 -> 25832 (-0.49 %)<br>
                      Spilled SGPRs: 0 -> 0 (0.00 %)<br>
                      Code Size: 2922632 -> 2930460 (0.27 %) bytes<br>
                      Max Waves: 1216 -> 1231 (1.23 %)<br>
                      <br>
                      Suggested-by: <Jason Ekstrand <a
                        href="mailto:jason@jlekstrand.net"
                        target="_blank" moz-do-not-send="true">jason@jlekstrand.net</a>><br>
                      Signed-off-by: Samuel Pitoiset <<a
                        href="mailto:samuel.pitoiset@gmail.com"
                        target="_blank" moz-do-not-send="true">samuel.pitoiset@gmail.com</a>><br>
                      ---<br>
                       src/amd/common/ac_nir_to_llvm.c | 8 ++++++++<br>
                       src/amd/vulkan/radv_shader.c    | 5 ++++-<br>
                       2 files changed, 12 insertions(+), 1 deletion(-)<br>
                      <br>
                      diff --git a/src/amd/common/ac_nir_to_llvm.c
                      b/src/amd/common/ac_nir_to_llvm.c<br>
                      index b25cc6a0a84..c46d98e6dd9 100644<br>
                      --- a/src/amd/common/ac_nir_to_llvm.c<br>
                      +++ b/src/amd/common/ac_nir_to_llvm.c<br>
                      @@ -3275,6 +3275,14 @@ static void
                      visit_intrinsic(struct ac_nir_context *ctx,<br>
                              case
                      nir_intrinsic_vulkan_resource_reindex:<br>
                                      result =
                      visit_vulkan_resource_reindex(ctx, instr);<br>
                                      break;<br>
                      +       case nir_intrinsic_load_vulkan_descriptor:
                      {<br>
                      +               LLVMValueRef values[2] = {<br>
                      +                       get_src(ctx,
                      instr->src[0]),<br>
                      +                       ctx->ac.i32_0,<br>
                      +               };<br>
                      +               result =
                      ac_build_gather_values(&ctx->ac, values,
                      2);<br>
                      +               break;<br>
                      +       }<br>
                              case nir_intrinsic_store_ssbo:<br>
                                      visit_store_ssbo(ctx, instr);<br>
                                      break;<br>
                      diff --git a/src/amd/vulkan/radv_shader.c
                      b/src/amd/vulkan/radv_shader.c<br>
                      index 19a807df199..2751302e8b9 100644<br>
                      --- a/src/amd/vulkan/radv_shader.c<br>
                      +++ b/src/amd/vulkan/radv_shader.c<br>
                      @@ -220,7 +220,6 @@
                      radv_shader_compile_to_nir(struct radv_device
                      *device,<br>
                                              }<br>
                                      }<br>
                                      const struct spirv_to_nir_options
                      spirv_options = {<br>
                      -                     
                       .lower_ubo_ssbo_access_to_offsets = true,<br>
                                              .caps = {<br>
                                                     
                      .descriptor_array_dynamic_indexing = true,<br>
                                                      .device_group =
                      true,<br>
                      @@ -306,6 +305,10 @@
                      radv_shader_compile_to_nir(struct radv_device
                      *device,<br>
                                      NIR_PASS_V(nir,
                      nir_lower_system_values);<br>
                                      NIR_PASS_V(nir,
                      nir_lower_clip_cull_distance_arrays);<br>
                                      NIR_PASS_V(nir, nir_lower_frexp);<br>
                      +<br>
                      +               NIR_PASS_V(nir,
                      nir_lower_explicit_io,<br>
                      +                         nir_var_mem_ubo |
                      nir_var_mem_ssbo,<br>
                      +                       
                       nir_address_format_32bit_index_offset);<br>
                    </blockquote>
                    <div><br>
                    </div>
                    <div>If you actually want to get SSBO access
                      optimization, you need to call this *after* your
                      first call to your main optimization loop. 
                      Otherwise, the change is basically just a no-op
                      which just shuffles around the way address
                      calculations are done a bit.</div>
                    <div><br>
                    </div>
                    <div>--Jason<br>
                    </div>
                    <div> </div>
                    <blockquote class="gmail_quote" style="margin:0px
                      0px 0px 0.8ex;border-left:1px solid
                      rgb(204,204,204);padding-left:1ex">         }<br>
                      <br>
                              /* Vulkan uses the separate-shader linking
                      model */<br>
                      -- <br>
                      2.21.0<br>
                      <br>
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                        moz-do-not-send="true">https://lists.freedesktop.org/mailman/listinfo/mesa-dev</a></blockquote>
                  </div>
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