<div dir="auto">R-b</div> <div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, Apr 24, 2019, 11:36 PM Marek Olšák <<a href="mailto:maraeo@gmail.com">maraeo@gmail.com</a>> wrote: </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Marek Olšák <<a href="mailto:marek.olsak@amd.com" target="_blank" rel="noreferrer">marek.olsak@amd.com</a>> need_cs_space may clear the buffer list. Fixes: 951d60f8cdc88 "radeonsi: delay adding BOs at the beginning of IBs until the first draw" --- src/gallium/drivers/radeonsi/si_compute.c | 6 +++--- src/gallium/drivers/radeonsi/si_state_draw.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index 2f444a3a1b8..541d7e6f118 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -878,40 +878,40 @@ static void si_launch_grid( if (sctx->has_graphics) { if (sctx->last_num_draw_calls != sctx->num_draw_calls) { si_update_fb_dirtiness_after_rendering(sctx); sctx->last_num_draw_calls = sctx->num_draw_calls; } si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE); } - if (sctx->bo_list_add_all_compute_resources) - si_compute_resources_add_all_to_bo_list(sctx); - /* Add buffer sizes for memory checking in need_cs_space. */ si_context_add_resource_size(sctx, &program->shader.bo->b.b); /* TODO: add the scratch buffer */ if (info->indirect) { si_context_add_resource_size(sctx, info->indirect); /* Indirect buffers use TC L2 on GFX9, but not older hw. */ if (sctx->chip_class <= VI && si_resource(info->indirect)->TC_L2_dirty) { sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; si_resource(info->indirect)->TC_L2_dirty = false; } } si_need_gfx_cs_space(sctx); + if (sctx->bo_list_add_all_compute_resources) + si_compute_resources_add_all_to_bo_list(sctx); + if (!sctx->cs_shader_state.initialized) si_initialize_compute(sctx); if (sctx->flags) si_emit_cache_flush(sctx); if (!si_switch_compute_shader(sctx, program, &program->shader, code_object, info->pc)) return; diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index d2c74152337..8e01e1b35e1 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1287,23 +1287,20 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i sctx->last_dirty_tex_counter = dirty_tex_counter; sctx->framebuffer.dirty_cbufs |= ((1 << sctx->framebuffer.state.nr_cbufs) - 1); sctx->framebuffer.dirty_zsbuf = true; si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer); si_update_all_texture_descriptors(sctx); } si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)); - if (sctx->bo_list_add_all_gfx_resources) - si_gfx_resources_add_all_to_bo_list(sctx); - /* Set the rasterization primitive type. * * This must be done after si_decompress_textures, which can call * draw_vbo recursively, and before si_update_shaders, which uses * current_rast_prim for this draw_vbo call. */ if (sctx->gs_shader.cso) rast_prim = sctx->gs_shader.cso->gs_output_prim; else if (sctx->tes_shader.cso) { if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE]) rast_prim = PIPE_PRIM_POINTS; @@ -1431,20 +1428,23 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i if (indirect->indirect_draw_count && si_resource(indirect->indirect_draw_count)->TC_L2_dirty) { sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false; } } } si_need_gfx_cs_space(sctx); + if (sctx->bo_list_add_all_gfx_resources) + si_gfx_resources_add_all_to_bo_list(sctx); + /* Since we've called si_context_add_resource_size for vertex buffers, * this must be called after si_need_cs_space, because we must let * need_cs_space flush before we add buffers to the buffer list. */ if (!si_upload_vertex_buffer_descriptors(sctx)) goto return_cleanup; /* Vega10/Raven scissor bug workaround. When any context register is * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR * registers must be written too. -- 2.17.1 _______________________________________________ mesa-dev mailing list <a href="mailto:mesa-dev@lists.freedesktop.org" target="_blank" rel="noreferrer">mesa-dev@lists.freedesktop.org</a> <a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev" rel="noreferrer noreferrer" target="_blank">https://lists.freedesktop.org/mailman/listinfo/mesa-dev</a></blockquote></div>