[Mesa-stable] [Mesa-dev] [PATCH] i965: Force X-tiling for 128 bpp formats on Sandybridge.

[Ian Romanick]

On 08/13/2013 05:47 PM, Chad Versace wrote:
> On 08/13/2013 05:45 PM, Ian Romanick wrote:
>> On 08/13/2013 03:37 PM, Kenneth Graunke wrote:
>>> 128 bpp formats are not allowed to be Y-tiled on any architectures
>>> except Gen7.
>>>
>>> +11 Piglits on Sandybridge (mostly regression fixes since the
>>> switch to Y-tiling).
>>>
>>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63867
>>
>> Also https://bugs.freedesktop.org/show_bug.cgi?id=64261?
>>
>>> Cc: Topi Pohjolainen <topi.pohjolainen at intel.com>
>>> Cc: Chad Versace <chad.versace at linux.intel.com>
>>> Cc: Paul Berry <stereotype441 at gmail.com>
>>> Cc: "9.2" <mesa-stable at lists.freedesktop.org>
>>> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
>>> ---
>>>   src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 +++++++++
>>>   1 file changed, 9 insertions(+)
>>>
>>> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
>>> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
>>> index d6643ca..86a2d53 100644
>>> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
>>> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
>>> @@ -468,6 +468,15 @@ intel_miptree_choose_tiling(struct brw_context
>>> *brw,
>>>      if (brw->gen < 6)
>>>         return I915_TILING_X;
>>>
>>> +   /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
>>> +    * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be
>>> either TileX
>>> +    *  or Linear."
>>> +    * 128 bits per pixel translates to 16 bytes per pixel.  This is
>>> necessary
>>> +    * all the way back to 965, but is explicitly permitted on Gen7.
>>> +    */
>>> +   if (brw->gen != 7 && mt->cpp >= 16)
>>> +      return I915_TILING_X;
>>
>> brw->gen < 7?  It seems reasonable to expect future hardware to not
>> re-introduce this restriction, right?
>
> Future hardware does re-introduce it.

Of course.  Lol.

Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>

> Reviewed-by: Chad Versace <chad.versace at linux.intel.com>