[Mesa-stable] [Mesa-dev] [PATCH 2/7] radeon/compute: Report a value for PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE

[Emil Velikov]

On 27/08/14 07:05, Dave Airlie wrote:
> I think Tom cc'ed the wrong stable maybe, not sure,
> 
> 10.2 doesn't have PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE, so this
> doesn't even build.
> 
> You might want to get a build system that builds all the drivers
> before applying and fixing up patches.
> 
The r600/radeonsi drivers were off my list last might due to the llvm
dependency. Updated everything and there should be no further problems.

Sorry about the breakage.

-Emil

> Dave.
> 
> On 27 August 2014 06:24, Emil Velikov <emil.l.velikov at gmail.com> wrote:
>> On 08/08/14 15:16, Tom Stellard wrote:
>>> CC: "10.2" <mesa-stable at lists.freedesktop.org>
>>> ---
>>>  src/gallium/drivers/r600/r600_pipe.c   | 11 ++++++++++-
>>>  src/gallium/drivers/radeonsi/si_pipe.c |  7 +++++++
>>>  2 files changed, 17 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
>>> index a08e70e..7ace671 100644
>>> --- a/src/gallium/drivers/r600/r600_pipe.c
>>> +++ b/src/gallium/drivers/r600/r600_pipe.c
>>> @@ -421,7 +421,16 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
>>>               /* XXX Isn't this equal to TEMPS? */
>>>               return 1; /* Max native address registers */
>>>       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
>>> -             return R600_MAX_CONST_BUFFER_SIZE;
>>> +             if (shader == PIPE_SHADER_COMPUTE) {
>>> +                     uint64_t max_const_buffer_size;
>>> +                     pscreen->get_compute_param(pscreen,
>>> +                             PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
>>> +                             &max_const_buffer_size);
>>> +                     return max_const_buffer_size;
>>> +
>>> +             } else {
>>> +                     return R600_MAX_CONST_BUFFER_SIZE;
>>> +             }
>>>       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
>>>               return R600_MAX_USER_CONST_BUFFERS;
>>>       case PIPE_SHADER_CAP_MAX_PREDS:
>>> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
>>> index 635b37d..791838f 100644
>>> --- a/src/gallium/drivers/radeonsi/si_pipe.c
>>> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
>>> @@ -327,6 +327,13 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
>>>               case PIPE_SHADER_CAP_DOUBLES:
>>>                       return 0; /* XXX: Enable doubles once the compiler can
>>>                                    handle them. */
>>> +             case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
>>> +                     uint64_t max_const_buffer_size;
>>> +                     pscreen->get_compute_param(pscreen,
>>> +                             PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
>>> +                             &max_const_buffer_size);
>>> +                     return max_const_buffer_size;
>>> +             }
>>>               default:
>>>                       return 0;
>>>               }
>>>
>>
>> Hello Tom,
>>
>> This patch does not apply cleanly to the 10.2 branch. I have resolved the
>> conflicts as below. Kindly let me know if I missed anything.
>>
>> -Emil
>>
>>
>> commit f40a0750a4fcd2c7f233b962a5e74166e12456ad
>> Author: Tom Stellard <thomas.stellard at amd.com>
>> Date:   Thu Aug 7 15:31:17 2014 -0400
>>
>>     radeon/compute: Report a value for PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
>>
>>     CC: "10.2" <mesa-stable at lists.freedesktop.org>
>>     (cherry picked from commit 72969e0efb7a5a011629c1001e81aa2329ede6b1)
>>
>>     Conflicts:
>>         src/gallium/drivers/r600/r600_pipe.c
>>         src/gallium/drivers/radeonsi/si_pipe.c
>>
>> diff --git a/src/gallium/drivers/r600/r600_pipe.c
>> b/src/gallium/drivers/r600/r600_pipe.c
>> index 0668b27..6ee4484 100644
>> --- a/src/gallium/drivers/r600/r600_pipe.c
>> +++ b/src/gallium/drivers/r600/r600_pipe.c
>> @@ -416,6 +416,17 @@ static int r600_get_shader_param(struct pipe_screen*
>> pscreen, unsigned shader, e
>>                 return 1; /* Max native address registers */
>>         case PIPE_SHADER_CAP_MAX_CONSTS:
>>                 return R600_MAX_CONST_BUFFER_SIZE;
>> +       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
>> +               if (shader == PIPE_SHADER_COMPUTE) {
>> +                       uint64_t max_const_buffer_size;
>> +                       pscreen->get_compute_param(pscreen,
>> +                               PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
>> +                               &max_const_buffer_size);
>> +                       return max_const_buffer_size;
>> +
>> +               } else {
>> +                       return R600_MAX_CONST_BUFFER_SIZE;
>> +               }
>>         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
>>                 return R600_MAX_USER_CONST_BUFFERS;
>>         case PIPE_SHADER_CAP_MAX_PREDS:
>> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
>> b/src/gallium/drivers/radeonsi/si_pipe.c
>> index ca8cea3..afb9bcb 100644
>> --- a/src/gallium/drivers/radeonsi/si_pipe.c
>> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
>> @@ -317,6 +317,13 @@ static int si_get_shader_param(struct pipe_screen*
>> pscreen, unsigned shader, enu
>>                 switch (param) {
>>                 case PIPE_SHADER_CAP_PREFERRED_IR:
>>                         return PIPE_SHADER_IR_LLVM;
>> +               case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
>> +                       uint64_t max_const_buffer_size;
>> +                       pscreen->get_compute_param(pscreen,
>> +                               PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
>> +                               &max_const_buffer_size);
>> +                       return max_const_buffer_size;
>> +               }
>>                 default:
>>                         return 0;
>>                 }
>>
>>
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